公开(公告)号：US09799658B2

公开(公告)日：2017-10-24

申请号：US14931073

申请日：2015-11-03

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kevin J. Torek

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01G4/008 ,  H01G4/005 ,  H01G4/06 ,  H01L21/311

CPC classification number: H01L27/10852 ,  H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/91

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

公开(公告)号：US20210193189A1

公开(公告)日：2021-06-24

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: G11C5/06 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20140120684A1

公开(公告)日：2014-05-01

申请号：US14147895

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kevin J. Torek

IPC: H01L49/02

CPC classification number: H01L27/10852 ,  H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/91

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Abstract translation: 形成电容器的方法包括在支撑材料内提供第一电容器电极。 第一电容器电极含有TiN，载体材料含有多晶硅。 使用含硫和含氟蚀刻化学法，相对于含TiN的第一电容器电极，选择性地对含多晶硅的支撑材料进行干式各向异性蚀刻。 在第一电容器电极的侧壁上形成电容器电介质，并且在电容器电介质上形成第二电容器电极。 公开了另外的方法。

公开(公告)号：US20160055973A1

公开(公告)日：2016-02-25

申请号：US14931073

申请日：2015-11-03

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kevin J. Torek

IPC: H01G4/06 ,  H01G4/008 ,  H01G4/005

CPC classification number: H01L27/10852 ,  H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/91

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Abstract translation: 形成电容器的方法包括在支撑材料内提供第一电容器电极。 第一电容器电极含有TiN，载体材料含有多晶硅。 使用含硫和含氟蚀刻化学法，相对于含TiN的第一电容器电极，选择性地对含多晶硅的支撑材料进行干式各向异性蚀刻。 在第一电容器电极的侧壁上形成电容器电介质，并且在电容器电介质上形成第二电容器电极。 公开了另外的方法。

公开(公告)号：US20220199123A1

公开(公告)日：2022-06-23

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: G11C5/06 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11355348B2

公开(公告)日：2022-06-07

申请号：US16847902

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kyle B. Campbell ,  Mario J. Di Cino ,  Aaron W. Freese ,  Alex Kogan ,  Kevin R. Shea

IPC: H01L21/30 ,  H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  G11C11/22 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating. After the removing, the pattern-interrupting second feature in the lower substrate material is used as a reference location to reckon which of the two different composition masking materials was used to make first spaces between the first features in an analysis area in the material that was above the lower substrate material or which of the two different composition masking materials was used to make second spaces between the first features in the analysis area that alternate with the first spaces. Structure independent of method is disclosed.

公开(公告)号：US10692727B2

公开(公告)日：2020-06-23

申请号：US16043869

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kyle B. Campbell ,  Mario J. Di Cino ,  Aaron W. Freese ,  Alex Kogan ,  Kevin R. Shea

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  G11C11/22 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating. After the removing, the pattern-interrupting second feature in the lower substrate material is used as a reference location to reckon which of the two different composition masking materials was used to make first spaces between the first features in an analysis area in the material that was above the lower substrate material or which of the two different composition masking materials was used to make second spaces between the first features in the analysis area that alternate with the first spaces. Structure independent of method is disclosed.

公开(公告)号：US11978527B2

公开(公告)日：2024-05-07

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L23/53257 ,  H01L23/5329

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230317800A1

公开(公告)日：2023-10-05

申请号：US17712776

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Dhirendra Dhananjay Vaidya ,  Lei Wei ,  Gurpreet Lugani ,  Sumeet C. Pandey

IPC: H01L29/40 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/402 ,  H01L27/11556 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from a memory-array region into a stair-step region. Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier. The individual laterally-spaced memory blocks comprise an intermediate region between the operative channel-material strings and the stair-step region. A dummy through-array-via (TAV) extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks. The dummy TAV is directly electrically coupled with the operative channel-material strings in its memory block. Other embodiments are disclosed.

公开(公告)号：US11328749B2

公开(公告)日：2022-05-10

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.