公开(公告)号：US11637040B2

公开(公告)日：2023-04-25

申请号：US17137135

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L23/28 ,  H01L21/78 ,  H01L23/00

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US20210249304A1

公开(公告)日：2021-08-12

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US20210193189A1

公开(公告)日：2021-06-24

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: G11C5/06 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230345721A1

公开(公告)日：2023-10-26

申请号：US17660767

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Frank Speetjens ,  Yucheng Wang ,  Brendan Flynn ,  S M Istiaque Hossain ,  Tom J. John ,  Jeremy Adams

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.

公开(公告)号：US20230058288A1

公开(公告)日：2023-02-23

申请号：US17979750

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US20220208609A1

公开(公告)日：2022-06-30

申请号：US17137135

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L21/78 ,  H01L23/00

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US20220199123A1

公开(公告)日：2022-06-23

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: G11C5/06 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11978527B2

公开(公告)日：2024-05-07

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L23/53257 ,  H01L23/5329

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230260840A1

公开(公告)日：2023-08-17

申请号：US18306137

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/28

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US11545391B2

公开(公告)日：2023-01-03

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.