MANAGING WRITE DISTURB FOR UNITS OF MEMORY IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20230244566A1

    公开(公告)日:2023-08-03

    申请号:US18296595

    申请日:2023-04-06

    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device. The operations performed by the processing device further include determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.

    TEMPERATURE-BASED ON BOARD PLACEMENT OF MEMORY DEVICES

    公开(公告)号:US20220019722A1

    公开(公告)日:2022-01-20

    申请号:US16930158

    申请日:2020-07-15

    Abstract: A quality rating for a memory device to be installed at a memory sub-system is determined, where the quality rating corresponds to a performance of the memory device at one or more operating temperatures. A determination is made whether the quality rating for the memory device satisfies a first quality rating condition associated with a first temperature zone of two or more temperature zones of the memory sub-system. Responsive to the determination that the quality rating for the memory device satisfies the first quality rating condition, the memory device is assigned to be installed at a first memory device socket of the first temperature zone.

    MANAGING WRITE DISTURB FOR UNITS OF MEMORY IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20230074538A1

    公开(公告)日:2023-03-09

    申请号:US17467826

    申请日:2021-09-07

    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit. The operations performed by the processing device further include determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies the second threshold criterion, performing a write scrub operation on the second memory unit.

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