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公开(公告)号：US11901014B2
公开(公告)日：2024-02-13
申请号：US17739741
申请日：2022-05-09
发明人： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号：US11854644B2
公开(公告)日：2023-12-26
申请号：US17550462
申请日：2021-12-14
发明人： Zhongguang Xu , Zhenlei Shen , Murong Lang
CPC分类号： G11C29/50004 , G06F3/0679
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.
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公开(公告)号：US20230360704A1
公开(公告)日：2023-11-09
申请号：US17739741
申请日：2022-05-09
发明人： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号：US11790998B2
公开(公告)日：2023-10-17
申请号：US17411278
申请日：2021-08-25
CPC分类号： G11C16/3418 , G11C16/08 , G11C16/102 , G11C16/24 , G11C16/26
摘要： A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
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公开(公告)号：US20230207041A1
公开(公告)日：2023-06-29
申请号：US18117583
申请日：2023-03-06
发明人： Zhenlei Shen , Tingjun Xie , Zhenming Zhou
CPC分类号： G11C29/42 , G06F11/1068 , G06F3/0619 , G06F3/0679 , G11C13/004 , G11C13/0069 , G06F3/0659 , G11C2029/0407
摘要： A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.
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公开(公告)号：US20230120838A1
公开(公告)日：2023-04-20
申请号：US18086580
申请日：2022-12-21
发明人： Tingjun Xie , Zhenming Zhou , Zhenlei Shen , Chih-Kuo Kao
摘要： A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.
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公开(公告)号：US11599272B2
公开(公告)日：2023-03-07
申请号：US17348226
申请日：2021-06-15
发明人： Zhenming Zhou , Seungjune Jeon , Zhenlei Shen
摘要： Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.
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公开(公告)号：US20220398022A1
公开(公告)日：2022-12-15
申请号：US17348226
申请日：2021-06-15
发明人： Zhenming Zhou , Seungjune Jeon , Zhenlei Shen
摘要： Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.
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公开(公告)号：US11520657B1
公开(公告)日：2022-12-06
申请号：US17445392
申请日：2021-08-18
发明人： Zhenlei Shen , Tingjun Xie , Frederick Adi , Wei Wang , Zhenming Zhou
摘要： A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.
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公开(公告)号：US20220365684A1
公开(公告)日：2022-11-17
申请号：US17302851
申请日：2021-05-13
发明人： Zhongguang Xu , Zhenlei Shen , Tingjun Xie , Seungjune Jeon , Murong Lang , Zhenming Zhou
摘要： Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.
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