公开(公告)号：US11925037B2

公开(公告)日：2024-03-05

申请号：US17804958

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/065 ,  H10B20/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/35

CPC classification number: H10B63/84 ,  H01L21/02074 ,  H01L21/76885 ,  H01L21/823885 ,  H01L25/0657 ,  H10B20/40 ,  H10B20/50 ,  H10B41/10 ,  H10B41/27 ,  H10B43/35 ,  H10B63/34

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

公开(公告)号：US20230335439A1

公开(公告)日：2023-10-19

申请号：US17720695

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  David A. Kewley ,  Deep Panjwani ,  Matthew Holland ,  Matthew J. King ,  Michael E. Koltonski ,  Tom J. John ,  Xiaosong Zhang ,  Yi Hu

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L23/53295 ,  H01L21/76832 ,  H01L27/11521

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

公开(公告)号：US11700729B2

公开(公告)日：2023-07-11

申请号：US17524913

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US11545391B2

公开(公告)日：2023-01-03

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US11362142B2

公开(公告)日：2022-06-14

申请号：US16877209

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H01L27/24 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/112 ,  H01L25/065 ,  H01L21/02

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

公开(公告)号：US20220067544A1

公开(公告)日：2022-03-03

申请号：US17005036

申请日：2020-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yi Hu ,  Dmitry Vengertsev ,  Zahra Hosseinimakarem ,  Jonathan D. Harms

IPC: G06N5/04 ,  G06T7/90 ,  G06T7/00 ,  G06T7/521 ,  G06N20/00 ,  G06T11/00

Abstract: An image or a spectrum of a surface may be acquired by a computing device, which may be included in a mobile device in some examples. The computing device may extract a measured spectrum from the image and generate a corrected spectrum of the surface. In some examples, the corrected spectrum may be generated to compensate for ambient light influence. The corrected spectrum may be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, the result is based, at least in part, on a comparison of the corrected spectrum to reference spectra. In some examples, the result is based, at least in part, on an inference of a machine learning model.

公开(公告)号：US20220035720A1

公开(公告)日：2022-02-03

申请号：US16943890

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Brooke Spencer ,  Jennifer F. Huckaby ,  Yi Hu ,  Deepti Verma

IPC: G06F11/30 ,  G06F11/32 ,  H05K7/20

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.

公开(公告)号：US11101210B2

公开(公告)日：2021-08-24

申请号：US16664618

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US11075219B2

公开(公告)日：2021-07-27

申请号：US16545375

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210057433A1

公开(公告)日：2021-02-25

申请号：US16545375

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.