公开(公告)号：US20170179382A1

公开(公告)日：2017-06-22

申请号：US15374957

申请日：2016-12-09

申请人： Microsemi SoC Corporation

发明人： John L. McCollum ,  Fethi Dhaoui ,  Frank W. Hawley

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/085 ,  G11C13/0011 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/11 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/54 ,  G11C2213/56 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.

公开(公告)号：US08723151B2

公开(公告)日：2014-05-13

申请号：US13840815

申请日：2013-03-15

申请人： Microsemi SoC Corporation

发明人： Jonathan Greene ,  Frank W. Hawley ,  John McCollum

IPC分类号： H01L29/02

CPC分类号： H03K19/1776 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H03K19/17724 ,  Y10S438/90

摘要： A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.

摘要翻译： 形成在集成电路中的电阻式随机存取存储单元包括包括阳极和阴极的第一电阻随机存取存储器件，包括阳极和阴极的第二电阻随机存取存储器件，第二电阻随机存取存储器件的阴极 连接到第一电阻式随机存取存储器件的阳极的编程晶体管，具有连接到编程电位节点的第一源极/漏极端子，连接到第一电阻随机存取存储器件的阳极的第二源极/漏极端子和 第二电阻随机存取存储器件的阴极和连接到编程使能点的栅极，以及至少一个开关晶体管，其栅极连接到第一电阻随机存取存储器件的阳极和第二电阻随机存取器件的阴极 访问存储设备。