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1.发明授权
公开(公告)号：US5324585A
公开(公告)日：1994-06-28
申请号：US903343
申请日：1992-06-24
申请人： Mihoko Akiyama , Keiichi Shiokawa , Youji Ide
发明人： Mihoko Akiyama , Keiichi Shiokawa , Youji Ide
CPC分类号： B41M5/52 , B41M5/41 , Y10S428/913 , Y10S428/914 , Y10T428/249987
摘要： An image receiving sheet for use in a thermal image transfer recording system, has an absorption coefficient (Ka) of 0.05 to 0.75 ml/m.sup.2 .multidot.(msec).sup.1/2 with respect to extra pure liquid paraffin at a pressure of 0.1 MPa when measured by the Bristow's Method (J.TAPPI No. 51-87). As such an image receiving sheet, an image receiving sheet having a recording surface with the product of (a) the absorption coefficient (Ka) with respect to the liquid paraffin (extra pure reagent) measured by the Bristow's Method (J.TAPPI No. 51-87) at a pressure of 0.1 MPa and (b) the gradient (fc) of a linear portion of a load curve obtained by a three-dimensional surface roughness analysis being in the range of 0.5 to 6.0 can be used. An image receiving sheet having a recording surface with the amount (V) of an ink transferred to the receiving sheet during 100 msec being in the range of 2.3 to 11.5 ml/m.sup.2 can also be used. The amount (V) is obtained from (a) the absorption coefficient (Ka) and (b) the surface roughness index (Vr) of the recording surface, which are measured by the Bristow's Method (J.TAPPI No. 51-87) at a pressure of 0.1 MPa, with respect to the liquid paraffin (extra pure reagent).
摘要翻译： 用于热图像转印记录系统的图像接收片相对于0.1MPa压力下的超纯液体石蜡的吸收系数（Ka）为0.05至0.75ml / m2×（msec）1/2，当通过 布里斯托法（J.TAPPI No.51-87）。 作为这样的图像接收片，具有通过Bristow方法测定的具有（a）吸收系数（Ka）相对于液体石蜡（超纯试剂）的记录面的记录面的图像接收片（J.TAPPI No. 51-87）和（b）通过三维表面粗糙度分析得到的负荷曲线的线性部分的梯度（fc）可以在0.5〜6.0的范围内。 也可以使用具有在100毫秒内转印到接收片材上的墨量（V）的记录表面的图像接收片材在2.3至11.5毫升/平方米的范围内。 数量（V）由（a）吸收系数（Ka）和（b）记录面的表面粗糙度指数（Vr）得到，其通过布里斯托法（J.TAPPI No.51-87）测量， 相对于液体石蜡（超纯试剂）为0.1MPa的压力。
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公开(公告)号：US5428372A
公开(公告)日：1995-06-27
申请号：US971212
申请日：1992-11-04
申请人： Mihoko Akiyama , Keiichi Shiokawa , Yoji Ide
发明人： Mihoko Akiyama , Keiichi Shiokawa , Yoji Ide
CPC分类号： B41M5/38278 , B41M5/52
摘要： A multiple-use thermal image transfer recording method includes the step of transferring a thermal image transfer ink component a plurality of times to an image-receiving medium from at least an identical portion of a thermal image transfer recording medium composed of a support and a thermal image transfer ink layer formed thereon, with the application of heat thereto. The thermal image transfer ink layer is composed of the thermal image transfer ink component mainly containing a coloring agent and a thermofusible material, and a porous resin component which is not thermally transferable, with both components having mutual releasability. The image-receiving medium has a recording surface, with the product of the absorption coefficient (Ka) of the recording surface measured by the Bristow Method (J. TAPPI. No. 51 - 87) at a pressure of 0.1 MPa, using an extra pure liquid paraffin, and the gradient (fc) of a linear portion of a load curve measured by a three-dimensional surface roughness analysis, being in the range of 2.0 to 6.0.
摘要翻译： 多用途热图像转印记录方法包括从热像传输记录介质的至少相同部分将热图像转印油墨组分多次转印到图像接收介质的步骤，所述热图像转印记录介质由支撑体和热 形成在其上的图像转印油墨层。 热转印油墨层由主要含有着色剂和热熔性材料的热转印油墨组分和不可热转印的多孔树脂组分组成，两种成分均具有相互释放性。 图像接收介质具有记录表面，其中利用Bristow方法（J.TAPPI.51-87）测量的记录表面的吸收系数（Ka）的乘积在0.1MPa的压力下，使用额外的 纯液体石蜡和通过三维表面粗糙度分析测量的负荷曲线的线性部分的梯度（fc）在2.0至6.0的范围内。
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公开(公告)号：US5336548A
公开(公告)日：1994-08-09
申请号：US992041
申请日：1992-12-17
申请人： Keiichi Shiokawa , Mihoko Akiyama , Yoji Ide , Yoshihiko Hiyoshi , Masahiro Sato , Kumi Surizaki
发明人： Keiichi Shiokawa , Mihoko Akiyama , Yoji Ide , Yoshihiko Hiyoshi , Masahiro Sato , Kumi Surizaki
CPC分类号： B41M5/42 , B41M5/38228 , Y10S428/913 , Y10S428/914 , Y10T428/249987 , Y10T428/25
摘要： A multiple-use thermal image transfer recording medium is composed of a heat-resistant support, a thermal image transfer layer formed on the heat-resistant support, which thermal image transfer layer is composed of a plurality of thermofusible ink layers overlaid on the heat-resistant support, and a porous resin layer formed on the thermal image transfer layer. The thermal image transfer layer contains a thermofusible ink component containing as the main components a coloring agent and a thermofusible material. The melt viscosity of the thermofusible ink component in each of the thermofusible ink layers is in such a relationship that the melt viscosity increases toward the heat-resistant support.
摘要翻译： 多用途热图像转印记录介质由耐热载体，形成在耐热载体上的热图像转印层组成，该热图像转印层由叠加在耐热支持体上的多个热熔性油墨层组成， 和形成在热转印层上的多孔树脂层。 热转印层包含含有作为主要成分的着色剂和热熔性材料的热熔性油墨成分。 每个热熔性油墨层中的热熔性油墨组分的熔融粘度是这样的关系：熔体粘度朝向耐热载体增加。
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公开(公告)号：US08638583B2
公开(公告)日：2014-01-28
申请号：US13621078
申请日：2012-09-15
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。
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公开(公告)号：US08004923B2
公开(公告)日：2011-08-23
申请号：US12683838
申请日：2010-01-07
IPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US06781431B2
公开(公告)日：2004-08-24
申请号：US10349033
申请日：2003-01-23
申请人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
发明人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
IPC分类号： G06F104
CPC分类号： H03K3/0315 , H02M3/07 , H03K3/013 , H03K3/70
摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。
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公开(公告)号：US08451678B2
公开(公告)日：2013-05-28
申请号：US13080114
申请日：2011-04-05
IPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20080298156A1
公开(公告)日：2008-12-04
申请号：US12170055
申请日：2008-07-09
IPC分类号： G11C5/14
CPC分类号： G11C29/48 , G11C29/12 , G11C29/12005
摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。
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公开(公告)号：US06424134B1
公开(公告)日：2002-07-23
申请号：US09759321
申请日：2001-01-16
申请人： Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Nobuyuki Fujii , Mihoko Akiyama , Mako Kobayashi
发明人： Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Nobuyuki Fujii , Mihoko Akiyama , Mako Kobayashi
IPC分类号： G05F316
摘要： A semiconductor device includes a constant voltage generation circuit generating a constant voltage commonly to reference voltages corresponding to a plurality of internal voltages. The plurality of reference voltages are generated from the common constant voltage. Thus, the semiconductor device for generating internal voltages is implemented, which allows reduction in layout area and decrease in test time for voltage adjustment.
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公开(公告)号：US07656736B2
公开(公告)日：2010-02-02
申请号：US11717717
申请日：2007-03-14
IPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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