公开(公告)号：US20070080854A1

公开(公告)日：2007-04-12

申请号：US10562988

申请日：2005-05-23

申请人： Yutaka Arayashiki ,  Sumio Saito ,  Masanori Ejima

发明人： Yutaka Arayashiki ,  Sumio Saito ,  Masanori Ejima

IPC分类号： G01S13/00 ,  G01S7/28

CPC分类号： G01S7/282 ,  G01S7/03 ,  H03B5/1203 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1231 ,  H03K3/70

摘要： The present invention, in order to enable intermittent output of an oscillation signal without essentially producing a leak in response to a pulse signal indicating a transmission timing of a radar wave, employs a configuration in which an operation of an oscillating unit (21) itself of a radar oscillator is alternately changed between an oscillating state and an oscillation stop state by a switch (30), not a configuration in which an output passage of an oscillation signal is switched to be opened and closed as in a conventional radar oscillator.

摘要翻译： 本发明为了能够根据表示雷达波的发送定时的脉冲信号实质地产生振荡信号的间歇输出，采用这样的结构，其中振荡单元（21）本身的操作 雷达振荡器通过开关（30）在振荡状态和振荡停止状态之间交替地变化，而不是如常规雷达振荡器那样将振荡信号的输出通道切换为打开和关闭的结构。

公开(公告)号：US20060132246A1

公开(公告)日：2006-06-22

申请号：US11303344

申请日：2005-12-16

申请人： Naveen Tiwari ,  Balwant Singh

发明人： Naveen Tiwari ,  Balwant Singh

IPC分类号： H03K3/03

CPC分类号： G06F1/04 ,  H03K3/0315 ,  H03K3/70

摘要： A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

摘要翻译： 无毛刺控制环形振荡器可以包括连接到门控和反相器级或装置的可编程延迟链。 可以在延迟链和门控和反相器级之间提供锁存或锁存装置，或者用于在禁止振荡器并将振荡器的输出设置为注册时钟状态时注册时钟状态的装置。

公开(公告)号：US20050218957A1

公开(公告)日：2005-10-06

申请号：US11146566

申请日：2005-06-07

申请人： Haluk Konuk ,  Vincent von Kaenel ,  Dai Le

发明人： Haluk Konuk ,  Vincent von Kaenel ,  Dai Le

IPC分类号： G06F1/06 ,  H03B19/00 ,  H03K3/03 ,  H03K3/70 ,  H03K5/01

CPC分类号： H03K3/70 ,  H03K3/0315

摘要： In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

摘要翻译： 在一个实施例中，时钟倍增器电路被耦合以接收输入信号，并被配置为产生输出时钟信号。 时钟倍增器电路被配置为响应于输入信号的边沿而在输出时钟信号上产生多个脉冲，其中脉冲具有与产生的脉冲数无关的宽度，并且独立于输入信号的频率 。 脉冲数可以选择。 在另一个实施例中，时钟倍增器电路包括电路和振荡器。 电路被配置为响应于控制信号而在时钟乘法器电路的输出时钟信号上产生多个脉冲。 振荡器被配置为产生具有宽度的流脉冲，其中电路被耦合以接收脉冲流。

公开(公告)号：US06914459B2

公开(公告)日：2005-07-05

申请号：US10857817

申请日：2004-06-01

申请人： Haluk Konuk ,  Vincent R. von Kaenel ,  Dai M. Le

发明人： Haluk Konuk ,  Vincent R. von Kaenel ,  Dai M. Le

IPC分类号： G06F1/06 ,  H03B19/00 ,  H03K3/03 ,  H03K3/70 ,  H03K5/01

CPC分类号： H03K3/70 ,  H03K3/0315

摘要： A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of the clock input signal. The clock multiplier circuit includes an oscillator and a logic circuit which generates a control signal for synchronization of the pulses to the control signal and to mask the pulses after a selected number of pulses have been output as the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the clock output signal in response to the control signal, while other pulses are masked.

摘要翻译： 时钟倍频器电路接收时钟输入信号并产生时钟输出信号。 时钟倍增器电路产生将用作时钟输出信号的多个脉冲，其中脉冲具有与产生的脉冲数无关的脉冲宽度，而与时钟输入信号的频率无关。 时钟倍频器电路包括一个振荡器和一个逻辑电路，该电路产生用于脉冲同步到控制信号的控制信号，并且在选择的脉冲数被输出作为时钟输出信号之后屏蔽脉冲。 时钟倍频器电路响应于控制信号而使多个未屏蔽的脉冲作为时钟输出信号输出，而其它脉冲被屏蔽。

公开(公告)号：US20040046594A1

公开(公告)日：2004-03-11

申请号：US10241070

申请日：2002-09-11

发明人： Haluk Konuk ,  Vincent R. von Kaenel ,  Dai M. Le

IPC分类号： H03B019/00

CPC分类号： H03K3/70 ,  H03K3/0315

摘要： In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

摘要翻译： 在一个实施例中，时钟倍增器电路被耦合以接收输入信号，并被配置为产生输出时钟信号。 时钟倍增器电路被配置为响应于输入信号的边沿而在输出时钟信号上产生多个脉冲，其中脉冲具有与产生的脉冲数无关的宽度，并且独立于输入信号的频率 。 脉冲数可以选择。 在另一个实施例中，时钟倍增器电路包括电路和振荡器。 电路被配置为响应于控制信号而在时钟乘法器电路的输出时钟信号上产生多个脉冲。 振荡器被配置为产生具有宽度的流脉冲，其中电路被耦合以接收脉冲流。

公开(公告)号：US20010050878A1

公开(公告)日：2001-12-13

申请号：US09899779

申请日：2001-07-05

发明人： Takeshi Yanagisawa

IPC分类号： G11C008/00 ,  G11C005/00

CPC分类号： G11C8/08 ,  G11C5/145 ,  H03K3/0315 ,  H03K3/70

摘要： A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.

摘要翻译： 提供具有升压电位生成电路的半导体存储器件（50）。 当字线（11）被激活时，升压电位产生电路可以向升压的电位节点提供电荷。 升压电位产生电路可以包括升压控制电路（5），升压电位检测电路（6），振荡电路（7）和升压电路（8）。 当命令解码器（1）指示字线可以被激活时，升压控制电路（5）可以产生升压控制信号。 响应于升压控制信号，升压电位检测电路（6）可以使得振荡器电路（7）使得升压电路（8）可以将电荷转移到升压电位节点。 这可以允许升压的电位节点具有足够的电荷，其可以在激活时提供给字线。

公开(公告)号：US3997800A

公开(公告)日：1976-12-14

申请号：US577957

申请日：1975-05-15

申请人： Alexander Bain

发明人： Alexander Bain

IPC分类号： H03K3/70 ,  H03K5/135 ,  H03K5/13

CPC分类号： H03K3/70 ,  H03K5/135

摘要： A flip-flop controlled clock gating system comprises a single-shot clock circuit including triggerable means effective to allow the passage of only one clock pulse from the clock input terminal to the output terminal; a clock inhibit circuit including a flip-flop network settable in a first condition enabling the passage of clock pulses from the input to the output terminal and STOP actuator means effective to actuate the flip-flop network to a second condition inhibiting the passage of such clock pulses; and a clock enable circuit including RUN actuator means effective when actuated to trigger the single-shot clock circuit to restore the flip-flop network to its first condition enabling the passage of clock pulses from the input terminal to its output terminal.

摘要翻译： 触发器控制时钟门控系统包括单触发时钟电路，其包括有效地允许从时钟输入端子到输出端子仅通过一个时钟脉冲的可触发装置; 时钟抑制电路，包括可在第一状态下设置的触发器网络，使得能够将时钟脉冲从输入端传递到输出端子，并且STOP致动器装置有效地将触发器网络驱动到阻止这种时钟的通过的第二状态 脉冲 以及包括RUN致动器装置的时钟使能电路，其在被致动以触发单稳时钟电路时有效，以将触发器网络恢复到其第一状态，使得能够将时钟脉冲从输入端子传递到其输出端子。

公开(公告)号：US20240204763A1

公开(公告)日：2024-06-20

申请号：US18540509

申请日：2023-12-14

申请人： Microchip Technology Incorporated

发明人： Yong Yuenyongsgool ,  Andreas Reiter ,  Stephen Bowling

IPC分类号： H03K7/08 ,  H03K3/70 ,  H03K7/10

CPC分类号： H03K7/08 ,  H03K3/70 ,  H03K7/10

摘要： A system and method is provided including a first pulse width modulation (PWM) generator circuit including a first timer to generate a first cycle count, a first configuration register to define characteristics of a first electrical pulse to be generated, and a trigger cycle count specifying a timing of a first trigger signal, and a first load enable input to load a new configuration value into the first configuration register, a second PWM generator circuit including a second timer to generate a second cycle count, a second configuration register to define characteristics of a second electrical pulse to be generated, a second load enable input to load a new configuration value into the second configuration register, and a load enable selector to selectively drive the second load enable input based on the first trigger signal.

公开(公告)号：US07332978B2

公开(公告)日：2008-02-19

申请号：US11303344

申请日：2005-12-16

申请人： Naveen Tiwari ,  Balwant Singh

发明人： Naveen Tiwari ,  Balwant Singh

IPC分类号： H03B27/00

CPC分类号： G06F1/04 ,  H03K3/0315 ,  H03K3/70

摘要： A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

摘要翻译： 无毛刺控制环形振荡器可以包括连接到门控和反相器级或装置的可编程延迟链。 可以在延迟链和门控和反相器级之间提供锁存或锁存装置，或者用于在禁止振荡器并将振荡器的输出设置为注册时钟状态时注册时钟状态的装置。

公开(公告)号：US06781431B2

公开(公告)日：2004-08-24

申请号：US10349033

申请日：2003-01-23

申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

IPC分类号： G06F104

CPC分类号： H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。