公开(公告)号：US20090047757A1

公开(公告)日：2009-02-19

申请号：US12253510

申请日：2008-10-17

申请人： Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

发明人： Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

IPC分类号： H01L21/336

CPC分类号： H01L29/458 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

摘要翻译： 在SOI衬底中形成的元件之间的隔离部分沟槽隔离的半导体器件中，针对晶体管的源极漏极的电阻降低和泄漏电流的降低。 在形成在掩埋氧化膜层（BOX层）上的SOI层中的隔离绝缘层规定的有源区域中形成MOS晶体管。 隔离绝缘层是尚未到达BOX层的部分沟槽隔离，源区和漏区包括彼此相互质量数不同的第一和第二杂质离子。

公开(公告)号：US20090127623A1

公开(公告)日：2009-05-21

申请号：US12354914

申请日：2009-01-16

申请人： Mikio TSUJIUCHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio TSUJIUCHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

摘要翻译： 在半导体器件中，在由SOI衬底，底层硅衬底，埋入绝缘体和 半导体层。 杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。 体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。 至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。 虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

公开(公告)号：US20110057275A1

公开(公告)日：2011-03-10

申请号：US12874894

申请日：2010-09-02

申请人： Mikio TSUJIUCHI ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

发明人： Mikio TSUJIUCHI ,  Yosuke Takeuchi ,  Kazuyuki Omori ,  Kenichi Mori

IPC分类号： H01L29/66 ,  H01L21/04

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/7833

摘要： To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion. The thickness of the sidewall portion is made greater than that of the bottom wall portion.

摘要翻译： 提供能够对选定的磁阻元件进行写入操作而不引起未选择的磁阻元件的故障的半导体器件和该半导体器件的制造方法。 半导体器件包括具有磁化自由层的磁存储元件，该磁化自由层的磁化方向是可变的，并且形成在引线互连和位于磁存储元件下方的位于第一方向上的数字线，并且能够改变磁化状态 磁化自由层由磁场产生。 数字线包括互连主体部分和覆盖互连体部分的底表面和侧表面并向上敞开的覆层。 包覆层包括覆盖互连主体部分的侧表面的侧壁部分和覆盖互连主体部分的底表面的底壁部分。 侧壁部分的厚度大于底壁部分的厚度。

公开(公告)号：US20110241140A1

公开(公告)日：2011-10-06

申请号：US13075681

申请日：2011-03-30

申请人： Mikio TSUJIUCHI ,  Masayoshi Tarutani ,  Yosuke Takeuchi

发明人： Mikio TSUJIUCHI ,  Masayoshi Tarutani ,  Yosuke Takeuchi

IPC分类号： H01L29/82

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device excellent in the magnetic shielding effect of blocking off external magnetic fields is provided. The semiconductor device includes: an interlayer insulating film so formed as to cover a switching element formed over a main surface of a semiconductor substrate; a flat plate-like lead wiring; a coupling wiring coupling the lead wiring and the switching element with each other; and a magnetoresistive element including a magnetization free layer the orientation of magnetization of which is variable and formed over the lead wiring. The semiconductor device has a wiring and another wiring through which the magnetization state of the magnetization free layer can be varied. In a memory cell area where multiple magnetoresistive elements are arranged, a first high permeability film arranged above the magnetoresistive elements is extended from the memory cell area up to a peripheral area that is an area other than the memory cell area.

摘要翻译： 提供了一种具有优异的阻挡外部磁场的磁屏蔽效果的半导体器件。 半导体器件包括：层间绝缘膜，其形成为覆盖形成在半导体衬底的主表面上的开关元件; 平板状引线; 使引线和开关元件彼此耦合的耦合布线; 以及包括磁化自由层的磁阻元件，其磁化方向可变并形成在引线布线上。 半导体器件具有布线和另一布线，通过该布线可以改变磁化自由层的磁化状态。 在布置有多个磁阻元件的存储单元区域中，布置在磁阻元件上方的第一高导磁率膜从存储单元区域延伸到作为存储单元区域以外的区域的外围区域。

公开(公告)号：US20070241401A1

公开(公告)日：2007-10-18

申请号：US11733363

申请日：2007-04-10

申请人： Mikio TSUJIUCHI

发明人： Mikio TSUJIUCHI

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/78615 ,  H01L27/0207 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： A MOS transistor including a source region, a drain region, and a gate electrode has first and second partial isolation regions in one-end gate region and the other-end gate region, respectively, with a first tap region provided adjacent to the first partial isolation region, and a second tap region provided adjacent to the second partial isolation region. A full isolation region is provided in the whole area around the first and second partial isolation regions, first and second tap regions, and source and drain regions.

摘要翻译： 包括源极区，漏极区和栅电极的MOS晶体管分别具有在一端栅极区域和另一端栅极区域中的第一和第二部分隔离区域，第一分接区域与第一部分 隔离区域和与第二部分隔离区域相邻设置的第二抽头区域。 在第一和第二部分隔离区域，第一和第二抽头区域以及源极和漏极区域周围的整个区域中提供完全隔离区域。

公开(公告)号：US20110163401A1

公开(公告)日：2011-07-07

申请号：US13048205

申请日：2011-03-15

申请人： Mikio TSUJIUCHI

发明人： Mikio TSUJIUCHI

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L27/228

摘要： Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed.

摘要翻译： 提供了一种具有MTJ元件的半导体器件，其能够在制造时有意地在一个方向上移动MRAM存储元件的开关电流的变化; 以及该装置的制造方法。 半导体器件具有水平长方形平面形状的下电极， 具有垂直长椭圆形平面形状的MTJ元件形成在下电极的右侧; 以及MTJ的上绝缘膜，其具有与下电极类似的水平长方形平面形状并且覆盖MTJ元件。 作为MTJ的上绝缘膜，采用用于向MTJ元件施加压应力或拉应力的压应力绝缘膜或拉应力绝缘膜。

公开(公告)号：US20090206425A1

公开(公告)日：2009-08-20

申请号：US12358840

申请日：2009-01-23

申请人： Mikio TSUJIUCHI

发明人： Mikio TSUJIUCHI

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L27/228

摘要： Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed.

摘要翻译： 提供了一种具有MTJ元件的半导体器件，其能够在制造时有意地在一个方向上移动MRAM存储元件的开关电流的变化; 以及该装置的制造方法。 半导体器件具有水平长方形平面形状的下电极; 具有垂直长椭圆形平面形状的MTJ元件形成在下电极的右侧; 以及MTJ的上绝缘膜，其具有与下电极类似的水平长方形平面形状并且覆盖MTJ元件。 作为MTJ的上绝缘膜，采用用于向MTJ元件施加压应力或拉应力的压应力绝缘膜或拉应力绝缘膜。