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公开(公告)号：US06658531B1
公开(公告)日：2003-12-02
申请号：US09614931
申请日：2000-07-12
申请人： Milivoje Aleksic , James Yee , Hon Ming Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Hon Ming Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译： 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。 根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。
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公开(公告)号：US06173367B2
公开(公告)日：2001-01-09
申请号：US09314210
申请日：1999-05-19
申请人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译： 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。 根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。
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公开(公告)号：US5574448A
公开(公告)日：1996-11-12
申请号：US436980
申请日：1995-05-08
申请人： Lih-Jyh Weng , John DeRoo , Michael Leis
发明人： Lih-Jyh Weng , John DeRoo , Michael Leis
CPC分类号： H03M5/145 , G06T9/005 , G11B20/1426 , H03M13/31
摘要： An encoding system uses a modified 8/9 rate modulation code to encode 8-bit data symbols into 9-bit cells in a conventional manner in accordance with the modified code and 9-bit ECC symbols into 10-bit cells by (i) encoding 8 bits of the symbol into a 9-bit cell in accordance with the modified code, and (ii) inserting into the 9-bit cell the remaining, that is, the non-encoded, bit of the ECC symbol. The system reproduces the 8-bit data symbols by decoding the 9-bit cells in a conventional manner in accordance with the modified code, and the 9-bit ECC symbols by (i) removing from the associated 10-bit cell the bit inserted during encoding, (ii) decoding the remaining 9 bits to reproduce 8 bits of the symbol, and (iii) inserting into the 8 bits the bit that was earlier removed. In an exemplary embodiment, the 8 least significant bits of the ECC symbol are encoded using the modified 8/9 rate code. The 9 bits produced by the code are used essentially as the first "c" bits and last "10-c" bits of a 10-bit cell. The most significant bit of the ECC symbol is included in the cell as the c+1.sup.st bit. The mapping of 8 bits to 9-bit cells is such that the inclusion of this c+1.sup.st bit does not violate the code's run length limitations, either within the cell or within a modulation code word, which is a concatenation of the cells. The system can similarly encode, using a modified n/m rate code, n-bit and (n+i)-bit symbols, where (n+i)
摘要翻译： 编码系统使用经修改的8/9速率调制码，以常规方式将8位数据符号根据经修改的代码和9位ECC符号编码为10比特单元，通过（i）编码 根据修改后的代码将符号的8位变换为9位单元，并且（ii）将9位单元中剩余的，即ECC符号的未编码位插入。 该系统通过根据修改的代码以常规方式对9位单元进行解码来再现8位数据符号，并且通过（i）从相关联的10位单元中删除插入的位的9位ECC符号来再现8位数据符号 编码，（ii）对剩余的9位进行解码以再现该符号的8位，以及（iii）在8位中插入较早去除的位。 在示例性实施例中，使用修改的8/9速率码对ECC符号的8个最低有效位进行编码。 由代码产生的9位实质上用作10位单元的第一个“c”位和最后一个“10-c”位。 ECC符号的最高有效位作为c + 1位包含在单元格中。 8位到9位单元的映射使得这个c + 1位的包含不会在单元内或在调制码字内，即单元格的级联中违反代码的运行长度限制。 该系统可以使用修正的n / m速率码，分别编码n位和（n + i）位符号，其中（n + i）
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公开(公告)号：US09239457B2
公开(公告)日：2016-01-19
申请号：US13548007
申请日：2012-07-12
申请人： Stephen R. Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
发明人： Stephen R. Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
CPC分类号： G02B26/02 , G02B26/005 , G02B26/023 , G09G3/3433 , G09G3/3466 , G09G2300/0465 , G09G2300/0473 , G09G2300/0838 , G09G2300/0842 , G09G2300/0857 , G09G2300/0866 , G09G2300/0876 , G09G2310/063
摘要： A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.
摘要翻译： 显示装置包括光调制器阵列。 每个光调制器具有被配置为将光调制器驱动到第一状态的第一致动器和被配置为将光调制器驱动到第二状态的第二致动器。 该显示装置还包括一个控制矩阵，对于阵列中的每个光调制器，包括单个致动电压互连。 致动电压互连被配置为将第一驱动电压施加到光调制器的第一致动器并将第二驱动电压施加到光调制器的第二致动器。 此外，致动电压互连被配置为控制向锁存电路施加数据电压以控制第一和第二驱动电压施加到第一和第二致动器。
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5.发明授权Stream based memory manager with function specific hardware logic for accessing data as a stream in memory 有权基于流的内存管理器，具有功能特定的硬件逻辑，用于以内存中的流式访问数据公开(公告)号：US07069397B2
公开(公告)日：2006-06-27
申请号：US10414431
申请日：2003-04-15
申请人： John DeRoo , Steve Metzger , Paul Phillips , Brian Ramelson
发明人： John DeRoo , Steve Metzger , Paul Phillips , Brian Ramelson
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： In one general aspect, a stream-based memory circuit is disclosed that includes physical storage elements and at least a first physical access port. A stream-based access controller is operatively connected to the physical storage elements and to the access port. The controller includes function-specific hardware logic operative to access data as streams in the physical memory in response to stream-based access commands at the access port.
摘要翻译： 在一个一般方面，公开了一种基于流的存储器电路，其包括物理存储元件和至少第一物理访问端口。 基于流的访问控制器可操作地连接到物理存储元件和访问端口。 控制器包括功能特定的硬件逻辑，用于响应于在接入端口处的基于流的访问命令，将数据作为数据流存储在物理存储器中。
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公开(公告)号：US20130176611A1
公开(公告)日：2013-07-11
申请号：US13548007
申请日：2012-07-12
申请人： Stephen Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
发明人： Stephen Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
IPC分类号： G02B26/02
CPC分类号： G02B26/02 , G02B26/005 , G02B26/023 , G09G3/3433 , G09G3/3466 , G09G2300/0465 , G09G2300/0473 , G09G2300/0838 , G09G2300/0842 , G09G2300/0857 , G09G2300/0866 , G09G2300/0876 , G09G2310/063
摘要： A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.
摘要翻译： 显示装置包括光调制器阵列。 每个光调制器具有被配置为将光调制器驱动到第一状态的第一致动器和被配置为将光调制器驱动到第二状态的第二致动器。 该显示装置还包括一个控制矩阵，对于阵列中的每个光调制器，包括单个致动电压互连。 致动电压互连被配置为将第一驱动电压施加到光调制器的第一致动器并将第二驱动电压施加到光调制器的第二致动器。 此外，致动电压互连被配置为控制向锁存电路施加数据电压以控制第一和第二驱动电压施加到第一和第二致动器。
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