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1.发明申请Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof 有权用于在图形系统中提供数据的存储器件及其方法和装置公开(公告)号：US20090307406A1
公开(公告)日：2009-12-10
申请号：US12429833
申请日：2009-04-24
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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2.发明授权Memory device for providing data in a graphics system and method and apparatus therof 有权用于在图形系统中提供数据的存储器件以及方法和装置公开(公告)号：US08924617B2
公开(公告)日：2014-12-30
申请号：US12429833
申请日：2009-04-24
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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公开(公告)号：US07543101B2
公开(公告)日：2009-06-02
申请号：US10075149
申请日：2002-02-14
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。
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公开(公告)号：US06546449B1
公开(公告)日：2003-04-08
申请号：US09347201
申请日：1999-07-02
IPC分类号： G06F1336
CPC分类号： G06F13/1684
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。
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公开(公告)号：US07430593B2
公开(公告)日：2008-09-30
申请号：US09971481
申请日：2001-10-05
申请人： Duane Mark Baldwin , James Horan Carey , Sean P. Cudmore , Irfan Asif Habib , Raymond M. Li , William Allen Medlyn , David Lynn Merbach
发明人： Duane Mark Baldwin , James Horan Carey , Sean P. Cudmore , Irfan Asif Habib , Raymond M. Li , William Allen Medlyn , David Lynn Merbach
IPC分类号： G06F15/177
CPC分类号： H04L67/1097 , H04L67/36
摘要： A storage area network (“SAN”) includes one or more digital data processors that are coupled for communication with one or more storage devices (e.g., LUNs) over an interconnect. The improvement provides a mechanism for hierarchically displaying, e.g., on the administrator console or other output device, portions of the SAN topology. It includes a process that generates for application to the output device a plurality of graphical object that represent “segments” of the SAN and/or components of the SAN, along with the interconnections between them. The process selectively responds to operator/administrator selection of any of the graphical objects that represent a segment by regenerating the display to depict the interconnected segments and/or components that make up that segment.
摘要翻译： 存储区域网络（“SAN”）包括一个或多个数字数据处理器，其被耦合用于通过互连与一个或多个存储设备（例如，LUN）进行通信。 该改进提供了用于在例如管理员控制台或其他输出设备上分级显示SAN拓扑的部分的机制。 它包括向应用程序生成表示SAN和/或SAN组件的“段”的多个图形对象以及它们之间的互连的过程。 该过程通过再生显示来选择代表段的任何图形对象的操作者/管理员选择，以描绘构成该段的互连段和/或组件。
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7.发明授权Storage area network methods and apparatus with coordinated updating of topology representation 失效具有拓扑表示协调更新的存储区域网络方法和装置公开(公告)号：US07890953B2
公开(公告)日：2011-02-15
申请号：US11258581
申请日：2005-10-24
申请人： Raymond M. Li , William Roy Yonker
发明人： Raymond M. Li , William Roy Yonker
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： H04L67/1097 , G06F11/0727 , H04L29/06 , H04L41/0213 , H04L41/0233 , H04L41/12 , H04L41/22 , H04L67/2819 , H04L69/329
摘要： A digital data processing apparatus of the type that manages a SAN includes a first queue with entries representing tasks and a second queue with entries representing data that correspond to those tasks. Data in the second queue is grouped in accord with the task to which they correspond. A manager service updates the internal representation of the SAN (e.g., the representation of the SAN topology) by executing the tasks in the first queue one at a time, for example, atomically using a single-threaded process.
摘要翻译： 管理SAN的类型的数字数据处理装置包括具有表示任务的条目的第一队列和具有表示与这些任务对应的数据的条目的第二队列。 第二个队列中的数据按照它们对应的任务进行分组。 管理员服务通过一次一个地执行第一个队列中的任务，例如原子地使用单线程进程来更新SAN的内部表示（例如，SAN拓扑的表示）。
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公开(公告)号：US07171624B2
公开(公告)日：2007-01-30
申请号：US09972092
申请日：2001-10-05
申请人： Duane Mark Baldwin , Allen Robert Heitman , Gregory John Knight , Raymond M. Li , David Lynn Merbach , William Roy Yonker
发明人： Duane Mark Baldwin , Allen Robert Heitman , Gregory John Knight , Raymond M. Li , David Lynn Merbach , William Roy Yonker
CPC分类号： H04L41/12 , G06F3/0481 , H04L29/06 , H04L41/22 , H04L67/1002 , H04L67/1097 , H04L69/329 , H04L2029/06054
摘要： A digital data processor of the type used, e.g., in management of a storage area network (SAN), executes a process (a “manager” process) to maintain a representation of the SAN topology or at least an attribute thereof. A graphical output device displays the SAN representation. A further process (a “user interface” process) controls the output device for purposes of displaying that representation. An interface element effects retrieval of the SAN representation, for example, in response to a request from the user interface process. It transmits that representation to the user interface process for display on the graphical output device.
摘要翻译： 例如在存储区域网络（SAN）的管理中使用的类型的数字数据处理器执行维护SAN拓扑的表示或至少其属性的过程（“管理者”过程）。 图形输出设备显示SAN表示。 为了显示该表示的目的，进一步的过程（“用户界面”过程）控制输出设备。 接口元素影响SAN表示的检索，例如响应于来自用户界面过程的请求。 它将该表示传输到用户界面过程，以在图形输出设备上显示。
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9.发明授权Video display method and apparatus with synchronized video playback and weighted frame creation 有权具有同步视频播放和加权帧创建的视频显示方法和装置公开(公告)号：US06297852B1
公开(公告)日：2001-10-02
申请号：US09223606
申请日：1998-12-30
申请人： Indra Laksono , Raymond M. Li
发明人： Indra Laksono , Raymond M. Li
IPC分类号： H04N974
CPC分类号： G09G5/12 , G09G2340/02 , G09G2340/125 , H04N5/04 , H04N5/4401 , H04N19/423 , H04N19/577 , H04N19/61 , H04N21/4307
摘要： A video display apparatus and method for displaying decoded video frames from an encoded video stream utilizes a display time difference determinator that detects a frame display time difference, on a per frame basis if desired, between a refresh rate based frame display time, and a video playback frame rate display time to generate frame display time difference data. This is done on a continuous basis to detect synchronization problems between video data that is to be displayed simultaneously with non-video data on a display device such as a progressive display screen. A pixel blender blends pixel data from an adjacent frame, such as an already reconstructed previous frame or next frame, to create a temporally adjusted frame based on the determined frame display time difference data.
摘要翻译： 一种用于从编码视频流中显示解码视频帧的视频显示装置和方法利用显示时间差确定器，该显示时间差确定器在基于刷新率的帧显示时间和视频之间检测帧显示时间差 播放帧率显示时间生成帧显示时差数据。 这是连续进行的，以检测与显示设备（例如逐行显示屏幕）上的非视频数据同时显示的视频数据之间的同步问题。 像素混合器将来自相邻帧（例如已经重构的先前帧或下一帧）的像素数据混合，以基于所确定的帧显示时差数据来创建时间上调整的帧。
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10.发明授权Methods and apparatus for launching device specific applications on storage area network components 失效在存储区域网络组件上启动设备特定应用的方法和装置公开(公告)号：US08060587B2
公开(公告)日：2011-11-15
申请号：US09972362
申请日：2001-10-05
申请人： Farhan Ahmad , Gary Thomas Axberg , Zhengwen He , Raymond M. Li , David Lynn Merbach , Gregory John Tevis , William Roy Yonker
发明人： Farhan Ahmad , Gary Thomas Axberg , Zhengwen He , Raymond M. Li , David Lynn Merbach , Gregory John Tevis , William Roy Yonker
IPC分类号： G06F15/173 , G06F15/177 , G06F15/16
CPC分类号： H04L41/06 , H04L41/0681 , H04L41/069 , H04L41/0803 , H04L41/0893 , H04L41/22 , H04L41/509 , H04L43/00 , H04L43/045 , H04L43/16 , H04L67/1097 , H04L69/329
摘要： A storage area network (SAN) of the type has a plurality of components including one or more digital data processors in communication with one or more storage devices via a switching fabric. An interface process, e.g., resident on a manager digital data processor, permits the operator/administrator to effect execution of at least a process residing on the manager and at least one process, such as a management application, residing on another SAN component.
摘要翻译： 该类型的存储区域网络（SAN）具有多个组件，包括经由交换结构与一个或多个存储设备通信的一个或多个数字数据处理器。 接口过程，例如驻留在管理者数字数据处理器上，允许操作员/管理员执行至少驻留在管理者上的过程和驻留在另一个SAN组件上的至少一个过程，例如管理应用程序的执行。
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