公开(公告)号：US07232756B2

公开(公告)日：2007-06-19

申请号：US10812003

申请日：2004-03-30

申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

摘要翻译： 提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。 示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。 后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍 合金金属如钽，表现出减少的团聚和改善的温度稳定性。

公开(公告)号：US07084061B2

公开(公告)日：2006-08-01

申请号：US10799788

申请日：2004-03-12

申请人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

发明人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.

摘要翻译： 提供了制造具有具有应变通道的MOS晶体管的半导体器件的方法。 该方法包括在半导体衬底的一部分处形成MOS晶体管。 MOS晶体管形成为具有彼此间隔开的源极/漏极区域和位于源极/漏极区域之间的沟道区域上方的栅极电极。 在具有MOS晶体管的半导体衬底上形成应力层。 然后应力层退火以将应力层的物理应力转变为拉伸应力或增加应力层的拉伸应力。

公开(公告)号：US07465617B2

公开(公告)日：2008-12-16

申请号：US11269599

申请日：2005-11-09

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

摘要翻译： 提供一种制造包括双间隔件的半导体器件的方法。 可以通过供应氮源气体在反应室中产生和保持氮气氛。 然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。 然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。 接下来，可以蚀刻氮化硅层直到氧化硅层露出。 由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。 结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

公开(公告)号：US20060057807A1

公开(公告)日：2006-03-16

申请号：US11269599

申请日：2005-11-09

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

公开(公告)号：US07005367B2

公开(公告)日：2006-02-28

申请号：US10612041

申请日：2003-07-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC分类号： H01L21/441

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

摘要翻译： 提供一种制造包括双间隔件的半导体器件的方法。 可以通过供应氮源气体在反应室中产生和保持氮气氛。 然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。 然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。 接下来，可以蚀刻氮化硅层直到氧化硅层露出。 由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。 结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

公开(公告)号：US20090250752A1

公开(公告)日：2009-10-08

申请号：US12457323

申请日：2009-06-08

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US20060163677A1

公开(公告)日：2006-07-27

申请号：US11386644

申请日：2006-03-22

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L29/94

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

公开(公告)号：US20060270205A1

公开(公告)日：2006-11-30

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

公开(公告)号：US07098123B2

公开(公告)日：2006-08-29

申请号：US10780244

申请日：2004-02-17

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

摘要翻译： 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US07544996B2

公开(公告)日：2009-06-09

申请号：US11498195

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。