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    Isolation for Semiconductor Devices
    5.
    发明申请
    Isolation for Semiconductor Devices 有权
    半导体器件隔离

    公开(公告)号：US20140061737A1

    公开(公告)日：2014-03-06

    申请号：US13598275

    申请日：2012-08-29

    申请人： Wen-I Hsu ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Wen-De Wang

    发明人： Wen-I Hsu ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Wen-De Wang

    IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L27/088

    CPC分类号： H01L27/14689 ,  H01L21/761 ,  H01L21/76237 ,  H01L27/1463 ,  H01L27/14643 ,  H01L29/0649

    摘要： A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.

    摘要翻译： 提供一种用于隔离半导体器件的系统和方法。 一个实施例包括从半导体器件的源极/漏极区域侧向移除的隔离区域，并且具有在源极/漏极区域之间的隔离注入物上延伸的介电材料。 可以通过在衬底上形成通过层的开口形成隔离区域，沿着开口的侧壁沉积电介质材料，在沉积之后将离子注入到衬底中，并用另一种电介质材料填充该开口。

    Multiple gate dielectric structures and methods of forming the same
    9.
    发明授权
    Multiple gate dielectric structures and methods of forming the same 有权
    多栅电介质结构及其形成方法

    公开(公告)号：US08685820B2

    公开(公告)日：2014-04-01

    申请号：US13207643

    申请日：2011-08-11

    申请人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    发明人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    IPC分类号： H01L21/336

    CPC分类号： H01L27/14614 ,  H01L27/14689

    摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.

    摘要翻译： 本公开提供了多栅极电介质半导体结构和形成这种结构的方法。 在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。 该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层 栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

    MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME
    10.
    发明申请
    MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME 有权
    多栅型电介质结构及其形成方法

    公开(公告)号：US20130037890A1

    公开(公告)日：2013-02-14

    申请号：US13207643

    申请日：2011-08-11

    申请人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    发明人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    IPC分类号： H01L21/28 ,  H01L29/78

    CPC分类号： H01L27/14614 ,  H01L27/14689

    摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.

    摘要翻译： 本公开提供了多栅极电介质半导体结构和形成这种结构的方法。 在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。 该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层 栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。