摘要:
A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.
摘要:
A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.
摘要:
A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要:
A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.
摘要:
A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要:
A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.
摘要:
A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.
摘要:
A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.
摘要:
A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.
摘要:
A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.