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1.发明授权Moving image communication device, moving image communication system and semiconductor integrated circuit used for communication of moving image 有权移动图像通信设备，运动图像通信系统和用于运动图像通信的半导体集成电路公开(公告)号：US08089514B2
公开(公告)日：2012-01-03
申请号：US12135645
申请日：2008-06-09
申请人： Minako Shimizu , Masahiro Ogawa , Taichi Nagata
发明人： Minako Shimizu , Masahiro Ogawa , Taichi Nagata
CPC分类号： H04L65/1059 , H04L65/403 , H04L65/602 , H04L65/80 , H04N19/51 , H04N21/2312 , H04N21/23418 , H04N21/2368 , H04N21/2383 , H04N21/2402 , H04N21/4341
摘要： A communication processor sets a storage request signal to be effective when it is judged that a packet cannot be transmitted and sets the storage request signal to be ineffective when it is judged that the packet can be transmitted. A data processor makes a buffer memory store encoded data therein when it is confirmed that the storage request signal is effective. The data processor reads the encoded data from the buffer memory and transmits the read encoded data to a packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is stored in the buffer memory. The data processor receives the encoded data from the encoder and transmits the received encoded data to the packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is not stored in the buffer memory.
摘要翻译： 当判断分组不能发送时，通信处理器将存储请求信号设置为有效，并且当判断出可以发送分组时，将存储请求信号设置为无效。 当确认存储请求信号有效时，数据处理器使缓冲存储器存储其中的编码数据。 当确认存储请求信号无效并且编码数据存储在缓冲存储器中时，数据处理器从缓冲存储器读取编码数据并将读取的编码数据发送到包发生器。 当确认存储请求信号无效并且编码数据未被存储在缓冲存储器中时，数据处理器从编码器接收编码数据并将接收到的编码数据发送到分组生成器。
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2.发明申请MOVING IMAGE COMMUNICATION DEVICE, MOVING IMAGE COMMUNICATION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT USED FOR COMMUNICATION OF MOVING IMAGE 有权移动图像通信设备，移动图像通信系统和用于通信移动图像的半导体集成电路公开(公告)号：US20080313683A1
公开(公告)日：2008-12-18
申请号：US12135645
申请日：2008-06-09
申请人： Minako Shimizu , Masahiro Ogawa , Taichi Nagata
发明人： Minako Shimizu , Masahiro Ogawa , Taichi Nagata
IPC分类号： H04N7/173
CPC分类号： H04L65/1059 , H04L65/403 , H04L65/602 , H04L65/80 , H04N19/51 , H04N21/2312 , H04N21/23418 , H04N21/2368 , H04N21/2383 , H04N21/2402 , H04N21/4341
摘要： A communication processor sets a storage request signal to be effective when it is judged that a packet cannot be transmitted and sets the storage request signal to be ineffective when it is judged that the packet can be transmitted. A data processor makes a buffer memory store encoded data therein when it is confirmed that the storage request signal is effective. The data processor reads the encoded data from the buffer memory and transmits the read encoded data to a packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is stored in the buffer memory. The data processor receives the encoded data from the encoder and transmits the received encoded data to the packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is not stored in the buffer memory.
摘要翻译： 当判断分组不能发送时，通信处理器将存储请求信号设置为有效，并且当判断出可以发送分组时，将存储请求信号设置为无效。 当确认存储请求信号有效时，数据处理器使缓冲存储器存储其中的编码数据。 当确认存储请求信号无效并且编码数据存储在缓冲存储器中时，数据处理器从缓冲存储器读取编码数据并将读取的编码数据发送到包发生器。 当确认存储请求信号无效并且编码数据未被存储在缓冲存储器中时，数据处理器从编码器接收编码数据并将接收到的编码数据发送到分组生成器。
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3.发明授权公开(公告)号：US07978198B2
公开(公告)日：2011-07-12
申请号：US11785414
申请日：2007-04-17
CPC分类号： H04N19/61 , G06F12/0207
摘要： An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in burst mode and writing the read data transfer units in a second image storage.
摘要翻译： 一种图像数据传送方法，包括以下步骤：（a）读取存储在第一图像存储器中并具有多个像素的二维图像的像素数据，每个像素的位置由第一和第二像素的坐标表示 通过扫描第二方向上的像素数据的数据传送单元来读取像素数据，其中每个数据传送单元由在第一方向上连续的预定数量的像素的数据形成; （b）将在步骤（a）读取的数据传送单元写入临时数据存储器，其中数据存储在由第一和第二地址的组合指定的位置处，数据传送单元以突发模式写入 临时数据存储，其中第一地址是连续的，而第二地址是固定的; 以及（c）从第一地址连续的区域读取临时数据存储器中写入的数据传送单元，同时在突发模式下读取固定第二地址的区域，并将读取的数据传送单元写入第二图像存储器。
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公开(公告)号：US07106225B2
公开(公告)日：2006-09-12
申请号：US11204378
申请日：2005-08-16
申请人： Taichi Nagata , Shinji Kitamura , Yasuharu Tanaka
发明人： Taichi Nagata , Shinji Kitamura , Yasuharu Tanaka
IPC分类号： H03M7/40
CPC分类号： H03M7/40
摘要： The present invention aims to provide a variable-length coding apparatus that achieves a short processing cycle without causing an increase in circuit scale.Such a variable-length coding apparatus judges whether a VLC table has a variable-length code (VLC) corresponding to a combination (Last, Run, Level), by using an LMAX and an RMAX for the combination (Last, Run, Level). Based on the result of the judgment, the variable-length coding apparatus generates and outputs a code assigned to the combination (Last, Run, Level).
摘要翻译： 本发明的目的在于提供一种在不引起电路规模的增加的情况下实现短的处理周期的可变长度编码装置。 这样的可变长度编码装置通过使用组合的LMAX和R MAX（Last，Run，Level）来判断VLC表是否具有与组合（Last，Run，Level）对应的可变长度代码（VLC） 。 基于判断结果，可变长度编码装置生成并输出分配给组合的代码（Last，Run，Level）。
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5.发明授权Variable length decoding device, variable length decoding method and image capturing system 有权可变长度解码装置，可变长度解码方法和图像采集系统公开(公告)号：US07929777B2
公开(公告)日：2011-04-19
申请号：US11798325
申请日：2007-05-11
申请人： Taichi Nagata , Shinji Kitamura
发明人： Taichi Nagata , Shinji Kitamura
摘要： A first data buffer stores LEVEL representing the size of a non-zero coefficient value of the variable length coded/run length coded data input from the outside. A write controller writes the LEVEL to the first data buffer in decoded order. An initial address calculator calculates the initial address of the LEVEL from the TotalCoeff and the number of zero coefficients of the total_zeros. An address holder determines and holds the address of the LEVEL corresponding to data based on the initial address and the number of zero coefficients by the run_before. A read controller reads the LEVEL from the first data buffer based on the address information. A selector selects the data of either the LEVEL stored in the first data buffer or the zero coefficients based on the address information. A post-stage processor post-stage processes the data selected by the selector.
摘要翻译： 第一数据缓冲器存储表示从外部输入的可变长度编码/游程长度编码数据的非零系数值的大小的LEVEL。 写控制器以解码的顺序将LEVEL写入第一数据缓冲器。 初始地址计算器从TotalCoeff和total_zeros的零系数的数量计算LEVEL的初始地址。 地址持有者基于run_before的初始地址和零系数的数量确定并保持对应于数据的LEVEL的地址。 读取控制器基于地址信息从第一数据缓冲器读取LEVEL。 选择器基于地址信息选择存储在第一数据缓冲器中的LEVEL数据或零系数。 后级处理器后级处理由选择器选择的数据。
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6.发明申请Variable length decoding device, variable length decoding method and image capturing system 有权可变长度解码装置，可变长度解码方法和图像采集系统公开(公告)号：US20070263939A1
公开(公告)日：2007-11-15
申请号：US11798325
申请日：2007-05-11
申请人： Taichi Nagata , Shinji Kitamura
发明人： Taichi Nagata , Shinji Kitamura
IPC分类号： G06K9/36
摘要： A first data buffer stores LEVEL representing the size of a non-zero coefficient value of the variable length coded/run length coded data input from the outside. A write controller writes the LEVEL to the first data buffer in decoded order. An initial address calculator calculates the initial address of the LEVEL from the TotalCoeff and the number of zero coefficients of the total_zeros. An address holder determines and holds the address of the LEVEL corresponding to data based on the initial address and the number of zero coefficients by the run_before. A read controller reads the LEVEL from the first data buffer based on the address information. A selector selects the data of either the LEVEL stored in the first data buffer or the zero coefficients based on the address information. A post-stage processor post-stage processes the data selected by the selector.
摘要翻译： 第一数据缓冲器存储表示从外部输入的可变长度编码/游程长度编码数据的非零系数值的大小的LEVEL。 写控制器以解码的顺序将LEVEL写入第一数据缓冲器。 初始地址计算器从TotalCoeff和total_zeros的零系数的数量计算LEVEL的初始地址。 地址持有者基于run_before的初始地址和零系数的数量确定并保持对应于数据的LEVEL的地址。 读取控制器基于地址信息从第一数据缓冲器读取LEVEL。 选择器基于地址信息选择存储在第一数据缓冲器中的LEVEL数据或零系数。 后级处理器后级处理由选择器选择的数据。
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公开(公告)号：US20070177015A1
公开(公告)日：2007-08-02
申请号：US11699567
申请日：2007-01-30
IPC分类号： H04N7/18
CPC分类号： H04N7/181
摘要： An image data processor converts an image signal into an image data. The multi-codec unit converts the image data into a transfer data. A communication unit receives a transfer request from an outside terminal device and transmits the transfer data to the outside terminal device. A time-sharing control unit controls to drive the image data processor and the multi-codec unit in a time-sharing manner in accordance with the transfer request. A transfer data selecting unit for selecting the transfer data corresponding to the transfer request from a group of the transfer data generated by the image data processing unit and the multi-codec unit which are controlled to drive in the time-sharing manner by the time-sharing management unit, and transmitting the selected transfer data to the communication unit
摘要翻译： 图像数据处理器将图像信号转换为图像数据。 多编解码器单元将图像数据转换为传送数据。 通信单元从外部终端设备接收传送请求，并将传送数据发送到外部终端设备。 分时控制单元根据转移请求控制以分时方式驱动图像数据处理器和多编解码器单元。 一种传输数据选择单元，用于从由图像数据处理单元和多编解码器单元生成的传送数据的一组中选择对应于传送请求的传送数据，该组由被分配时间分配的方式控制， 共享管理单元，以及将所选择的传送数据发送到通信单元
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8.发明申请Variable-length coding method, variable-length coding device and imaging system 有权可变长度编码方法，可变长度编码装置和成像系统公开(公告)号：US20060273939A1
公开(公告)日：2006-12-07
申请号：US11444438
申请日：2006-06-01
申请人： Yasuharu Tanaka , Shinji Kitamura , Taichi Nagata
发明人： Yasuharu Tanaka , Shinji Kitamura , Taichi Nagata
IPC分类号： H03M7/40
CPC分类号： H03M7/40 , H04N19/159 , H04N19/91
摘要： A VLC mode judgment section performs judgment on whether or not a received group (Last, Run, Level) exists in a VLC table and then performs judgment on which one of a first escape mode, a second escape more and a third escape mode is suitable. According to a judgment result of the VLC mode judgment section, an FLC processing section or a coding mode selection section performs variable-length coding using selected one of the received group (Last, Run, Level), a group generated in the first escape mode, and a group generated by the second escape group or fixed-length coding using a third escape mode.
摘要翻译： VLC模式判断部分对VLC表中是否存在接收到的组（Last，Run，Level）进行判断，然后判断第一逃避模式，第二逃逸模式和第三逃生模式中的哪一个是适合的 。 根据VLC模式判断部分的判断结果，FLC处理部分或编码模式选择部分使用所接收的组（Last，Run，Level）中选择的一个进行可变长度编码， 以及由第二转义组生成的组或使用第三逃逸模式的固定长度编码。
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公开(公告)号：US20060055571A1
公开(公告)日：2006-03-16
申请号：US11204378
申请日：2005-08-16
申请人： Taichi Nagata , Shinji Kitamura , Yasuhara Tanaka
发明人： Taichi Nagata , Shinji Kitamura , Yasuhara Tanaka
IPC分类号： H03M7/40
CPC分类号： H03M7/40
摘要： The present invention aims to provide a variable-length coding apparatus that achieves a short processing cycle without causing an increase in circuit scale. Such a variable-length coding apparatus judges whether a VLC table has a variable-length code (VLC) corresponding to a combination (Last, Run, Level), by using an LMAX and an RMAX for the combination (Last, Run, Level). Based on the result of the judgment, the variable-length coding apparatus generates and outputs a code assigned to the combination (Last, Run, Level).
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公开(公告)号：US20060044165A1
公开(公告)日：2006-03-02
申请号：US11214343
申请日：2005-08-30
申请人： Kentaro Takakura , Shinji Kitamura , Taichi Nagata
发明人： Kentaro Takakura , Shinji Kitamura , Taichi Nagata
IPC分类号： H03M7/46
CPC分类号： H03M7/40
摘要： A variable length decoding device for decoding variable length coding data and run length coding data according to the present invention comprises a variable length decoding unit 3 for serially decoding the variable length coding data and the run length coding data inputted from outside in a state in which “RUN” representing number of “0” and “LEVEL” representing a magnitude of a coefficient value are combined, a data buffer 4 for storing the “LEVEL”, address retainers 5 and 6 for retaining an address of the “LEVEL” corresponding to the “RUN” based on the number of “0” indicated by the “RUN”, a write control unit 7 for writing the “LEVEL” in the data buffer 4 based on the information of the address retainers, and a read control unit 8 for reading the “LEVEL” from the data buffer 4 based on the information of the address retainers.
摘要翻译： 根据本发明的用于解码可变长度编码数据和游程长度编码数据的可变长度解码装置包括：可变长度解码单元3，用于将可变长度编码数据和从外部输入的游程长度编码数据串行解码， 组合表示系数值大小的“0”和“LEVEL”的“RUN”，存储“LEVEL”的数据缓冲器4，用于保持对应于“LEVEL”的“LEVEL”的地址的地址保持器5和6 基于“RUN”指示的“0”的数量的“RUN”，根据地址保持器的信息将数据缓冲器4中的“LEVEL”写入的写入控制部7，以及读取控制部8 用于基于地址保持器的信息从数据缓冲器4读取“LEVEL”。
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