ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    1.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
    静电放电保护装置

    公开(公告)号:US20120146151A1

    公开(公告)日:2012-06-14

    申请号:US13040415

    申请日:2011-03-04

    IPC分类号: H01L23/62

    摘要: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    摘要翻译: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface
    2.
    发明申请
    High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface 有权
    用于混合电压I / O接口的高耐压功率轨道ESD钳位电路

    公开(公告)号:US20080232013A1

    公开(公告)日:2008-09-25

    申请号:US12134061

    申请日:2008-06-05

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0266

    摘要: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

    摘要翻译: 用于静电放电(ESD)保护的电路包括电阻器,与电阻器串联连接的电容器,包括栅极的第一晶体管,栅极连接到第一电源,通过电阻向栅极提供第一电压,第一 端子连接到第一电源,第二晶体管包括栅极,栅极连接到第二电源,第二电源提供小于第一电压的第二电压,第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管,栅极连接到第二电源,第三晶体管的第一端子连接到第二晶体管的第二端子,第二端子连接到第二晶体管, 参考电压不同于第一电压和第二电压。

    Transient voltage detection circuit
    3.
    发明授权
    Transient voltage detection circuit 有权
    瞬态电压检测电路

    公开(公告)号:US08116049B2

    公开(公告)日:2012-02-14

    申请号:US12625449

    申请日:2009-11-24

    IPC分类号: H02H3/22

    CPC分类号: H02H9/046 H02H1/0007

    摘要: The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

    摘要翻译: 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管,电容器和检测节点。 晶体管与电容器耦合,检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此,形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。

    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
    4.
    发明授权
    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface 有权
    用于混合电压I / O接口的高耐压电源轨ESD钳位电路

    公开(公告)号:US07397280B2

    公开(公告)日:2008-07-08

    申请号:US11366143

    申请日:2006-03-02

    IPC分类号: H03K19/0175

    CPC分类号: H01L27/0266

    摘要: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

    摘要翻译: 用于静电放电(ESD)保护的电路包括电阻器,与电阻器串联连接的电容器,包括栅极的第一晶体管,栅极连接到第一电源,通过电阻向栅极提供第一电压,第一 端子连接到第一电源,第二晶体管包括栅极,栅极连接到第二电源,第二电源提供小于第一电压的第二电压,第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管,栅极连接到第二电源,第三晶体管的第一端子连接到第二晶体管的第二端子,第二端子连接到第二晶体管, 参考电压不同于第一电压和第二电压。

    High-voltage tolerant power rail electrostatic discharge clamp circuit
    5.
    发明授权
    High-voltage tolerant power rail electrostatic discharge clamp circuit 有权
    高耐压电力轨道静电放电钳位电路

    公开(公告)号:US07283342B1

    公开(公告)日:2007-10-16

    申请号:US11428571

    申请日:2006-07-05

    IPC分类号: H02H9/00 H02H3/20 H02H3/22

    CPC分类号: H01L27/0285

    摘要: A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.

    摘要翻译: 提出了一种高耐压电源轨ESD钳位电路,其中电路器件可以在没有栅极氧化可靠性问题的工艺限制的三倍大的高电源电压下安全工作。 此外,ESD检测电路用于通过基板触发技术有效地提高整个ESD保护功能。 由于仅使用低电压(1 * VDD)器件来实现高电压(3 * VDD)公差的目标,所以提出的设计为具有混合电压接口的芯片提供了具有成本效益的电源轨ESD保护解决方案。

    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
    6.
    发明申请
    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface 有权
    用于混合电压I / O接口的高耐压电源轨ESD钳位电路

    公开(公告)号:US20070205800A1

    公开(公告)日:2007-09-06

    申请号:US11366143

    申请日:2006-03-02

    IPC分类号: H03K19/003

    CPC分类号: H01L27/0266

    摘要: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

    摘要翻译: 用于静电放电(ESD)保护的电路包括电阻器,与电阻器串联连接的电容器,包括栅极的第一晶体管,栅极连接到第一电源,通过电阻向栅极提供第一电压,第一 端子连接到第一电源,第二晶体管包括栅极,栅极连接到第二电源,第二电源提供小于第一电压的第二电压,第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管,栅极连接到第二电源,第三晶体管的第一端子连接到第二晶体管的第二端子,第二端子连接到第二晶体管, 参考电压不同于第一电压和第二电压。

    TRANSIENT VOLTAGE DETECTION CIRCUIT
    7.
    发明申请
    TRANSIENT VOLTAGE DETECTION CIRCUIT 有权
    瞬态电压检测电路

    公开(公告)号:US20100315754A1

    公开(公告)日:2010-12-16

    申请号:US12625449

    申请日:2009-11-24

    IPC分类号: H02H3/22

    CPC分类号: H02H9/046 H02H1/0007

    摘要: The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

    摘要翻译: 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管,电容器和检测节点。 晶体管与电容器耦合,检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此,形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。

    HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT
    8.
    发明申请
    HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT 有权
    高压容许电源线ESD钳位电路

    公开(公告)号:US20070230073A1

    公开(公告)日:2007-10-04

    申请号:US11428571

    申请日:2006-07-05

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0285

    摘要: A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.

    摘要翻译: 提出了一种高耐压电源轨ESD钳位电路,其中电路器件可以在没有栅极氧化可靠性问题的工艺限制的三倍大的高电源电压下安全工作。 此外,ESD检测电路用于通过基板触发技术有效地提高整个ESD保护功能。 由于仅使用低电压(1 * VDD)器件来实现高电压(3 * VDD)公差的目标,所以提出的设计为具有混合电压接口的芯片提供了具有成本效益的电源轨ESD保护解决方案。

    Electrostatic discharge protection device
    9.
    发明授权
    Electrostatic discharge protection device 有权
    静电放电保护装置

    公开(公告)号:US08507946B2

    公开(公告)日:2013-08-13

    申请号:US13040415

    申请日:2011-03-04

    摘要: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    摘要翻译: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    System-level ESD detection circuit
    10.
    发明授权
    System-level ESD detection circuit 有权
    系统级ESD检测电路

    公开(公告)号:US08067952B2

    公开(公告)日:2011-11-29

    申请号:US12283868

    申请日:2008-04-18

    IPC分类号: G01R31/02 G01R31/26

    CPC分类号: G01R19/0053 G01R31/002

    摘要: An ESD detection circuit for detecting a level of an ESD voltage on a power rail is provided. The ESD detection circuit includes a resistive component, a diode unit, and a controller. The resistive component is coupled between a detection node and a ground node corresponding to the power rail. The diode unit is coupled between the power rail and the detection node in a forward direction toward the power rail. The controller, coupled to the detection node, is used for determining the level of the ESD voltage based on the voltage of the detection node and the breakdown voltage of the diode unit.

    摘要翻译: 提供了用于检测电力轨上的ESD电压电平的ESD检测电路。 ESD检测电路包括电阻元件,二极管单元和控制器。 电阻分量耦合在检测节点和对应于电力轨的接地节点之间。 二极管单元在电力轨道和检测节点之间朝向电力轨道向前方向耦合。 耦合到检测节点的控制器用于基于检测节点的电压和二极管单元的击穿电压来确定ESD电压的电平。