公开(公告)号：US08344416B2

公开(公告)日：2013-01-01

申请号：US12777672

申请日：2010-05-11

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

公开(公告)号：US08378422B2

公开(公告)日：2013-02-19

申请号：US12609803

申请日：2009-10-30

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US20100200922A1

公开(公告)日：2010-08-12

申请号：US12609803

申请日：2009-10-30

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US07384802B2

公开(公告)日：2008-06-10

申请号：US11438603

申请日：2006-05-22

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L21/00

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US07081662B1

公开(公告)日：2006-07-25

申请号：US11199833

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/00 ,  H01L29/73

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US07372083B2

公开(公告)日：2008-05-13

申请号：US11199662

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/72

CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

摘要翻译： 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US20070037355A1

公开(公告)日：2007-02-15

申请号：US11438603

申请日：2006-05-22

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L21/331

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US20070034956A1

公开(公告)日：2007-02-15

申请号：US11199662

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L23/62

CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

摘要翻译： 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US08288822B2

公开(公告)日：2012-10-16

申请号：US13172555

申请日：2011-06-29

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC分类号： H01L27/06

CPC分类号： H01L27/0259 ,  H01L27/1203

摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

公开(公告)号：US20110254091A1

公开(公告)日：2011-10-20

申请号：US13172555

申请日：2011-06-29

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC分类号： H01L27/12

CPC分类号： H01L27/0259 ,  H01L27/1203

摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。