公开(公告)号：US4240140A

公开(公告)日：1980-12-16

申请号：US973462

申请日：1978-12-26

申请人： John P. Stafford ,  Minoru Inoshita ,  Gerald N. Winfrey

发明人： John P. Stafford ,  Minoru Inoshita ,  Gerald N. Winfrey

IPC分类号： G06F13/24 ,  G06F3/153 ,  G06F13/34 ,  G09G1/16 ,  G09G5/00 ,  G06F9/36 ,  G06F9/46

CPC分类号： G09G5/001 ,  G06F13/34 ,  G06F3/153 ,  G09G2360/18

摘要： A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.

摘要翻译： 阴极射线管显示终端系统包括中央处理器子系统和多个某些外围子系统，所有这些外围子系统都共同地耦合到系统总线。 中央处理器子系统中的装置接收来自某些外围子系统的中断请求信号，并且在预定的优先级基础上，根据请求的某些外围子系统中哪一个具有最高优先级来修改由中央处理器子系统生成的地址。 称为矢量地址的修改地址指向存储在存储器子系统中的固件子程序，存储器子系统也耦合到系统总线，并且处理来自最高优先级的cetain外设子系统的中断。 耦合到系统总线的其它外围子系统产生也应用于中央处理器系统中的装置的单个中断信号。 产生单个中断信号的最高优先级的其他外围子系统通过向用于修改由中央处理子系统生成的地址的设备发送地址信号来响应来自中央处理器子系统的中断确认信号，以产生向量地址。

公开(公告)号：US4558412A

公开(公告)日：1985-12-10

申请号：US557379

申请日：1983-12-01

申请人： Minoru Inoshita ,  Gerald N. Winfrey

发明人： Minoru Inoshita ,  Gerald N. Winfrey

IPC分类号： G06F13/30 ,  G06F13/00

CPC分类号： G06F13/30

摘要： In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA bus cycle.

摘要翻译： 在包括中央处理器子系统，存储器子系统和多个外围子系统的终端系统中，所有终端系统都共同连接到系统总线，系统总线定时分为多个固定时间，包括中央处理器（CPU）总线周期 和多个直接存储器访问（DMA）总线周期。 中央处理器子系统在CPU总线周期期间与存储器子系统进行通信，并且外设子系统在DMA总线周期内与存储器子系统进行通信。 特定的外设子系统被分配给特定的DMA通道。 这些DMA通道在特定的DMA总线周期上与存储器子系统进行通信，这些周期以旋转优先级运行，第一个DMA总线周期在先前的DMA总线周期的最后一个DMA总线周期之后发生。 多个外围子系统以菊花链方式连接到特定DMA通道，其中最靠近系统总线的外设子系统具有最高优先级。 具有最高优先级的外设子系统可以被布线以在与存储器通信之后放弃所分配的DMA总线周期，或者“分配”分配的DMA总线周期。

公开(公告)号：US4225942A

公开(公告)日：1980-09-30

申请号：US973364

申请日：1978-12-26

申请人： Frederick E. Kobs ,  Joseph L. Ryan ,  Minoru Inoshita ,  Gerald N. Winfrey

发明人： Frederick E. Kobs ,  Joseph L. Ryan ,  Minoru Inoshita ,  Gerald N. Winfrey

IPC分类号： G06F13/24 ,  G06F3/153 ,  G06F13/34 ,  G09G1/16 ,  G09G5/00 ,  G06F9/46

CPC分类号： G09G5/001 ,  G06F13/34 ,  G06F3/153 ,  G09G2360/18

摘要： A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.

摘要翻译： 微处理器控制的阴极射线管显示系统具有多个共同连接到系统总线的外围设备。 每个外围设备中的设备激活单个中断信号。 对所有设备的单个确认响应信号使得中断设备能够将其地址信号放置在系统总线上，从而启动用于使中断设备与系统一起操作的固件程序。

公开(公告)号：US4414645A

公开(公告)日：1983-11-08

申请号：US296932

申请日：1981-08-27

申请人： Joseph L. Ryan ,  Gerald N. Winfrey

发明人： Joseph L. Ryan ,  Gerald N. Winfrey

IPC分类号： G09G1/02 ,  G09G5/42 ,  G06F3/153

CPC分类号： G09G5/42 ,  G09G1/02

摘要： Each row of video information in a display memory includes a linking character code followed by address codes representative of the address location in such display memory of a first data character of a next row of video information displayed on the CRT screen. Both row insertions and deletions may be accommodated by changing address codes under firmware control without requiring the complete rewrite of video information stored in the display memory.

摘要翻译： 显示存储器中的每行视频信息包括链接字符代码，随后是代表显示在CRT屏幕上的下一行视频信息的第一数据字符的这种显示存储器中的地址位置的地址代码。 可以通过在固件控制下改变地址代码来适应行插入和删除，而不需要完全重写存储在显示存储器中的视频信息。