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公开(公告)号：US4225942A
公开(公告)日：1980-09-30
申请号：US973364
申请日：1978-12-26
CPC分类号： G09G5/001 , G06F13/34 , G06F3/153 , G09G2360/18
摘要： A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.
摘要翻译： 微处理器控制的阴极射线管显示系统具有多个共同连接到系统总线的外围设备。 每个外围设备中的设备激活单个中断信号。 对所有设备的单个确认响应信号使得中断设备能够将其地址信号放置在系统总线上，从而启动用于使中断设备与系统一起操作的固件程序。
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2.发明授权CRT display terminal priority interrupt apparatus for generating vectored addresses 失效用于产生向量地址的CRT显示终端优先中断装置
公开(公告)号：US4240140A
公开(公告)日：1980-12-16
申请号：US973462
申请日：1978-12-26
CPC分类号： G09G5/001 , G06F13/34 , G06F3/153 , G09G2360/18
摘要： A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.
摘要翻译： 阴极射线管显示终端系统包括中央处理器子系统和多个某些外围子系统，所有这些外围子系统都共同地耦合到系统总线。 中央处理器子系统中的装置接收来自某些外围子系统的中断请求信号，并且在预定的优先级基础上，根据请求的某些外围子系统中哪一个具有最高优先级来修改由中央处理器子系统生成的地址。 称为矢量地址的修改地址指向存储在存储器子系统中的固件子程序，存储器子系统也耦合到系统总线，并且处理来自最高优先级的cetain外设子系统的中断。 耦合到系统总线的其它外围子系统产生也应用于中央处理器系统中的装置的单个中断信号。 产生单个中断信号的最高优先级的其他外围子系统通过向用于修改由中央处理子系统生成的地址的设备发送地址信号来响应来自中央处理器子系统的中断确认信号，以产生向量地址。
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公开(公告)号：US4558412A
公开(公告)日：1985-12-10
申请号：US557379
申请日：1983-12-01
申请人： Minoru Inoshita , Gerald N. Winfrey
发明人： Minoru Inoshita , Gerald N. Winfrey
CPC分类号： G06F13/30
摘要： In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA bus cycle.
摘要翻译： 在包括中央处理器子系统，存储器子系统和多个外围子系统的终端系统中，所有终端系统都共同连接到系统总线，系统总线定时分为多个固定时间，包括中央处理器（CPU）总线周期 和多个直接存储器访问（DMA）总线周期。 中央处理器子系统在CPU总线周期期间与存储器子系统进行通信，并且外设子系统在DMA总线周期内与存储器子系统进行通信。 特定的外设子系统被分配给特定的DMA通道。 这些DMA通道在特定的DMA总线周期上与存储器子系统进行通信，这些周期以旋转优先级运行，第一个DMA总线周期在先前的DMA总线周期的最后一个DMA总线周期之后发生。 多个外围子系统以菊花链方式连接到特定DMA通道，其中最靠近系统总线的外设子系统具有最高优先级。 具有最高优先级的外设子系统可以被布线以在与存储器通信之后放弃所分配的DMA总线周期，或者“分配”分配的DMA总线周期。
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4.发明授权Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data 失效多处理器计算机系统，包括用于动态分配可变数据的所有权的方法和装置
公开(公告)号：US5963973A
公开(公告)日：1999-10-05
申请号：US796309
申请日：1997-02-07
CPC分类号： G06F12/0833
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：处理器目录，用于存储标识驻留在高速缓冲存储器中的信息块的识别字，并且包括指示本地CPU在块上的写许可权限的状态字段;输出缓冲器 用于存储驻留在CPU不具有的高速缓冲存储器中的块的识别字，并且寻求写许可，并且用于选择性地将标识字和无效命令发送到CPU总线上;输入缓冲器，用于存储所有最近的识别字 响应于比较器感测比较条件（通常指示另一个CPU对另一个CPU的写入许可的请求），比较器用于将输出缓冲器中的识别字与输入缓冲器和控制逻辑中的标识进行比较 相同的块，本地CPU也要求写入许可），用于aborti 纳入本地CPU的写许可请求并建立重试过程。
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5.发明授权Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel 失效用于检测由并行操作的双处理单元产生的双精度结果之间的差异的装置
公开(公告)号：US5422837A
公开(公告)日：1995-06-06
申请号：US168114
申请日：1993-12-14
CPC分类号： G06F11/1641 , G06F11/1064
摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.
摘要翻译： 为了在包含重复的BPU的CPU中验证完整性的数据操作结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，则采用两个高速缓存单元。 每个缓存单元专用于处理半字节的信息，并且包含高度可靠的数据验证逻辑，而不需要从每个BPU提供双字宽输出总线。 通过将每个缓存单元专用于处理半字节的信息来获得降低每个VLSI芯片的引导计数的这个特征。 每个缓存单元包括逐位比较电路，用于在单精度操作的情况下验证从两个BPU接收的半字节结果，并且在双精度操作的情况下，一个高速缓存单元采用相同的逐位比较， 位比较电路，用于两个缓存单元，验证从两个BPU接收到的结果奇偶校验位，并因此验证半字节结果。
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6.发明授权Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache 失效在使用个别中央处理器单元和共享缓存的专用高速缓存的多处理器计算机系统中的信息块传输管理
公开(公告)号：US6006309A
公开(公告)日：1999-12-21
申请号：US768552
申请日：1996-12-18
CPC分类号： G06F12/0811 , G06F12/0859
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和包括一对半块操作数缓冲器的高速缓存控制器，每个缓存器被分成四个块段。 操作数缓冲器组被耦合以在输入多路复用器的控制下选择性地在四分之一块区段中从CPU总线接收所请求的信息块，并且还被耦合以在输出多路复用器的控制下将接收的四分之一块段 CPU并接收到高速缓冲存储器的完整块。
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7.发明授权Private cache miss and access management in a multiprocessor system with shared memory 失效具有共享内存的多处理器系统中的专用缓存未命中和访问管理
公开(公告)号：US5829029A
公开(公告)日：1998-10-27
申请号：US769682
申请日：1996-12-18
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F12/0811 , G06F12/0831 , G06F12/084
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.
摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓存存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器 以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识 组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于 块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。
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公开(公告)号：US5649090A
公开(公告)日：1997-07-15
申请号：US708965
申请日：1991-05-31
CPC分类号： G06F12/0817 , G06F11/1064 , G06F11/1044 , G06F11/1402 , G06F11/1405 , G06F11/2268
摘要： A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
摘要翻译： 容错计算机系统包括至少两个中央处理单元，每个中央处理单元具有高速缓冲存储器和奇偶校验错误检测器，该奇偶校验错误检测器适于在从高速缓冲存储器读取和写入高速缓冲存储器的信息块中检测奇偶校验错误，并且如果 奇偶校验错误被检测到。 系统总线将CPU耦合到具有奇偶纠错设施的系统控制单元，并且存储器总线将SCU耦合到主存储器。 分布在CPU上的错误恢复控制功能（包括服务处理器和操作系统软件）响应于发送CPU中的读取奇偶校验错误标志和接收CPU中的写入奇偶校验错误标志与虹吸管 用于经由SCU（其中给定故障块被校正）将故障块从发送CPU传送到主存储器的操作，并且用于随后在重试时将校正的存储器块从主存储器传送到接收CPU。
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