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公开(公告)号:US20100148350A1
公开(公告)日:2010-06-17
申请号:US12606504
申请日:2009-10-27
CPC分类号: H01L23/49816 , H01L21/561 , H01L23/3128 , H01L23/5385 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/18 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/15173 , H01L2924/15183 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/3511 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.
摘要翻译: 在包括堆叠在作为下封装的第一半导体封装上的作为上封装的第二半导体封装的POP型半导体器件中,形成在第一半导体封装的第一布线基板上的多个主表面侧焊盘分布地布置在两者上 作为位于第一布线基板的主表面的中心部分的边界的芯片安装区域的侧面,从而允许采用直通成型方法。 因此,形成在第一半导体封装中的第一布线基板的主表面上的第一密封体作为下封装从第一布线基板的一个第二侧朝向相同基板的另一第二侧的中心部分延伸。