公开(公告)号：US06594785B1

公开(公告)日：2003-07-15

申请号：US09561270

申请日：2000-04-28

申请人： Roger L. Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson ,  James L. DePenning ,  Michael L. Haupt ,  Donald Kalvestrand ,  Daniel S. Tokoly ,  Frederick G. Fellenser ,  Maria A. Liedman

发明人： Roger L. Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson ,  James L. DePenning ,  Michael L. Haupt ,  Donald Kalvestrand ,  Daniel S. Tokoly ,  Frederick G. Fellenser ,  Maria A. Liedman

IPC分类号： H02H305

CPC分类号： G06F11/0772 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0793

摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

摘要翻译： 当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。 也可以由非故障单元进行连续处理。 支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。

公开(公告)号：US06434641B1

公开(公告)日：2002-08-13

申请号：US09322405

申请日：1999-05-28

申请人： Michael L. Haupt ,  Mitchell A. Bauman

发明人： Michael L. Haupt ,  Mitchell A. Bauman

IPC分类号： G06F1208

CPC分类号： G06F12/0828 ,  G06F2212/621

摘要： A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure. According to one aspect of the invention, all deferred requests requesting access to the same main memory address are stored as a linked list of requests in the temporary storage structure. Requests are processed by main memory in a first-in, first-out manner such that the oldest requests are completed before more recently-received requests. According to another aspect of the invention, the request management system further handles I/O overwrite operations wherein a peripheral device is allowed to overwrite requested addresses within the main memory even though the most recent copy of the data associated with some of the overwritten memory addresses is stored within ones of the cache memories. To process the I/O overwrite operations in a manner that preserves data coherency, the I/O overwrite requests are deferred in a manner that is similar to cache-initiated requests. Specifically, I/O overwrite requests made to an address associated with any previously-deferred I/O overwrite or cache-initiated requests are deferred until all such previously-deferred requests are processed by main memory.

公开(公告)号：US5625892A

公开(公告)日：1997-04-29

申请号：US363446

申请日：1994-12-22

申请人： Mitchell A. Bauman ,  Michael L. Haupt

发明人： Mitchell A. Bauman ,  Michael L. Haupt

IPC分类号： G06F1/32 ,  G06F11/34 ,  H04B7/005 ,  H04L1/18

CPC分类号： H04W52/267 ,  G06F1/32 ,  G06F11/3433 ,  G06F2201/81 ,  G06F2201/88 ,  H04L1/1854 ,  Y02B60/165 ,  Y02B60/50

摘要： A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level. Hysteresis is provided to allow time for the power sourcing circuitry to recharge before discontinuing the delays.

摘要翻译： 一种用于通过临时延迟多个数据传输接口来降低功耗的动态功耗降低装置。 数据传输接口只有在极少数据数据传输一段时间的罕见情况下才被延迟。 监视活动数据传输接口的数量，根据活动数据传输接口的数量，计数值递增或递减。 如果计数值达到阈值，则表示预定时间段内的数据传输次数异常高，因此功耗高。 在预定时间段内数据传输数量高的情况下，将延迟注入到握手周期中，以将数据确认信号从数据接收器延迟到数据发送器。 当数据传输接口活动降低到正常水平时，延迟被停止。 提供迟滞，以便在停止延迟之前为供电电路充电的时间。

公开(公告)号：US06189078B1

公开(公告)日：2001-02-13

申请号：US09218813

申请日：1998-12-22

申请人： Mitchell A. Bauman ,  Michael L. Haupt

发明人： Mitchell A. Bauman ,  Michael L. Haupt

IPC分类号： G06F1300

CPC分类号： G06F12/0808

摘要： A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device. A purge command is issued to the first device to invalidate the copy of the requested data segment in the first local memory. Upon issuance of the purge command to the first device, a purge acknowledge response is delivered to the second device, where the purge acknowledge response provides an indication that the copy of the requested data in the first local memory has been invalidated. The second device is prohibited from releasing any modified data until the purge acknowledge response is received.

摘要翻译： 提供了一种用于减少事务处理系统中的数据传输延迟的系统和方法。 该系统包括多个具有相关联的本地存储器的设备，以及具有用于存储数据段的主存储模块和用于维持存储在主存储模块和本地存储器中的每个数据段的所有权状态的目录存储器的监控存储器模块 。 第二设备请求存储在第一设备的第一本地存储器中的数据段。 所请求的数据段的数据传输请求从第二设备传送到监控存储器模块，其中数据传输请求包括请求许可修改所请求的数据段的标识符。 在接收到数据传输请求时，所请求的数据和数据传输响应被传送到第二设备，其中数据传输响应向所述第二设备提供所请求的数据段的修改特权。 向第一设备发出清除命令以使第一本地存储器中所请求的数据段的副本无效。 当向第一设备发出清除命令时，清除确认响应被传递到第二设备，其中清除确认响应提供指示第一本地存储器中所请求的数据的副本已经被无效。 在接收到清除确认响应之前，禁止第二个设备释放任何修改的数据。

公开(公告)号：US6167489A

公开(公告)日：2000-12-26

申请号：US218811

申请日：1998-12-22

申请人： Mitchell A. Bauman ,  Roger Lee Gilbertson ,  Michael L. Haupt

发明人： Mitchell A. Bauman ,  Roger Lee Gilbertson ,  Michael L. Haupt

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4239

摘要： A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first device to a second local memory in a second device in a transaction processing system that includes a main memory to provide supervisory storage capability for the transaction processing system, and a directory storage for maintaining ownership status of each data segment of the main memory. A data transfer of a requested data segment is requested by the second device to obtain the requested data segment stored in the first local memory of the first device. The requested data segment is removed from the first local memory in response to the data transfer request, and is directly transferred to the second local memory of the second device. The requested data segment is also transferred to the main memory, and to the directory storage where the ownership status can be revised to reflect a change of ownership from the first device to the second device. The direct transfer of the requested data segment between the first and second devices occurs independently of the transfer of the requested data segment from the first device to the main memory and directory storage.

摘要翻译： 一种用于在具有本地存储器的设备之间提供数据段的直接传送的系统和方法，而不需要首先将数据传送到中央监控存储器以维持高速缓存一致性。 在交易处理系统中的第二设备中，从第一设备的第一本地存储器到第二本地存储器执行直接数据传输，所述交易处理系统包括为交易处理系统提供监控存储能力的主存储器，以及用于维护 主内存的每个数据段的所有权状态。 所请求的数据段的数据传送由第二设备请求以获得存储在第一设备的第一本地存储器中的所请求的数据段。 响应于数据传输请求，请求的数据段从第一本地存储器中移除，并且被直接传送到第二设备的第二本地存储器。 所请求的数据段也被传送到主存储器以及可以修改所有权状态的目录存储器，以反映从第一设备到第二设备的所有权变化。 所请求的数据段在第一和第二设备之间的直接传送不依赖于所请求的数据段从第一设备到主存储器和目录存储的传送。

公开(公告)号：US07343515B1

公开(公告)日：2008-03-11

申请号：US10954842

申请日：2004-09-30

申请人： R. Lee Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson

发明人： R. Lee Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0712 ,  G06F11/0724

摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.

摘要翻译： 公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。 一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。 在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。 当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。 受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应 记忆以不涉及恢复操作的正常方式。

公开(公告)号：US07167955B1

公开(公告)日：2007-01-23

申请号：US10745372

申请日：2003-12-23

申请人： Justin S. Neils ,  John S. Jensen ,  Mitchell A. Bauman ,  Eugene A. Rodi ,  Bart E. Reigstad

发明人： Justin S. Neils ,  John S. Jensen ,  Mitchell A. Bauman ,  Eugene A. Rodi ,  Bart E. Reigstad

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F11/1008 ,  G06F2212/1032

摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.

摘要翻译： 用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。 在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块 响应于存储器请求确定所请求的数据条目的下一目录状态。 为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。 另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。 选择器的输出可能会写入目录存储。

公开(公告)号：US06587931B1

公开(公告)日：2003-07-01

申请号：US09001598

申请日：1997-12-31

申请人： Mitchell A. Bauman ,  Eugene A. Rodi ,  Douglas E. Morrissey

发明人： Mitchell A. Bauman ,  Eugene A. Rodi ,  Douglas E. Morrissey

IPC分类号： G06F1208

CPC分类号： G06F12/0817 ,  G06F12/0886 ,  G06F2212/621

摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.

摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

公开(公告)号：US06477620B1

公开(公告)日：2002-11-05

申请号：US09467190

申请日：1999-12-20

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

IPC分类号： G06F1208

CPC分类号： G06F12/0813 ,  G06F12/0811

摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.

摘要翻译： 公开了一种用于分级，多级存储器的数据旁路系统。 旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。 优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。 为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。 可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。

公开(公告)号：US06356991B1

公开(公告)日：2002-03-12

申请号：US09001390

申请日：1997-12-31

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson

IPC分类号： G06F1206

CPC分类号： G06F12/0607 ,  G06F12/0292

摘要： A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, GRA reprogramming may occur while memory operations continue within other non-associated address ranges. Additionally, address interleaving may be selected for certain ones of the address ranges, whereas a non-interleaving scheme may be selected for other address ranges.

摘要翻译： 提供了一种用于模块化主存储器的可编程地址转换系统。 该系统使用一个或多个通用寄存器阵列（GRA）实现，其中每个GRA对系统内的预定地址范围进行逻辑到物理地址转换。 使用逻辑地址的预定比特来寻址与逻辑地址范围相关联的GRA。 然后将从GRA读取的数据位代替逻辑地址的预定位以形成物理地址。 以这种方式，物理存储器的不连续可寻址组可以被映射到可选择的相邻地址范围。 通过在GRA地址内包含用于寻址连续逻辑地址的N个逻辑地址位，提供地址转换机制，其可被编程为在2路和2N路地址交错之间执行。 可以动态地重新编程每个GRA以适应可能发生的变化的存储器条件，例如当由于错误而从系统逻辑地移除存储器的范围时。 此外，当存储器操作在其他非关联地址范围内继续时，可能会发生GRA重新编程。 另外，可以针对某些地址范围来选择地址交织，而对于其他地址范围可以选择非交织方案。