公开(公告)号：US20090067255A1

公开(公告)日：2009-03-12

申请号：US12204207

申请日：2008-09-04

申请人： Mikio OGAWA ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Mikio OGAWA ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

摘要翻译： 写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。 对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。 无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。 在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

公开(公告)号：US07808821B2

公开(公告)日：2010-10-05

申请号：US12204207

申请日：2008-09-04

申请人： Mikio Ogawa ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Mikio Ogawa ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

摘要翻译： 写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。 对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。 无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。 在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

公开(公告)号：US20090073764A1

公开(公告)日：2009-03-19

申请号：US12211495

申请日：2008-09-16

申请人： Mitsuaki HONMA ,  Yoshikazu Takeyama

发明人： Mitsuaki HONMA ,  Yoshikazu Takeyama

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

摘要翻译： 存储单元阵列包括存储多个位的多个存储单元。 读出放大器检测从从存储单元阵列中选择的存储单元读取的数据。 在用于验证写入数据的写入验证操作时，当存储器单元的阈值电压超过预定检查点时，数据控制单元将要写入存储器单元的写入数据转换成指示剩余的数量的数据 写入电压施加次数，仅在执行写入电压施加操作时仅反转一次数据的数据，并且改变次数的数据的定义从而进行减法运算。

公开(公告)号：US07855915B2

公开(公告)日：2010-12-21

申请号：US12211495

申请日：2008-09-16

申请人： Mitsuaki Honma ,  Yoshikazu Takeyama

发明人： Mitsuaki Honma ,  Yoshikazu Takeyama

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

摘要翻译： 存储单元阵列包括存储多个位的多个存储单元。 读出放大器检测从从存储单元阵列中选择的存储单元读取的数据。 在用于验证写入数据的写入验证操作时，当存储器单元的阈值电压超过预定检查点时，数据控制单元将要写入存储器单元的写入数据转换成指示剩余的数量的数据 写入电压施加次数，仅在执行写入电压施加操作时仅反转一次数据的数据，并且改变次数的数据的定义从而进行减法运算。

公开(公告)号：US07663960B2

公开(公告)日：2010-02-16

申请号：US12133701

申请日：2008-06-05

申请人： Toshihiro Suzuki ,  Yoshikazu Takeyama

发明人： Toshihiro Suzuki ,  Yoshikazu Takeyama

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C16/0483 ,  G11C16/12 ,  H02M3/073 ,  H02M2003/075

摘要： A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit.

摘要翻译： 从输出端子切换并输出多个设定电压的电压供给电路具有升压电路，其升压从电源供给的电压，并将该电压输出到输出端子; 电压检测电路，当检测到从升压电路输出的电压不低于设定电压时，输出第一标志信号，当检测到从升压电路输出的电压不低于频率调整电压时，输出第二标志 设定低于设定电压; 以及控制电路，其根据设定电压和电压检测电路的输出信号来控制升压电路的动作。

公开(公告)号：US07642760B2

公开(公告)日：2010-01-05

申请号：US11757605

申请日：2007-06-04

申请人： Yoshikazu Takeyama

发明人： Yoshikazu Takeyama

IPC分类号： G05F1/40 ,  G05F1/56

CPC分类号： G05F1/465 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

摘要： The disclosure concerns a power supply circuit comprising a voltage converter receiving an external voltage and outputting an internal voltage; a first switch and a second switch connected between an output of the voltage converter and a constant voltage source; a resistor provided between the first switch and the second switch, and dividing the internal voltage; a comparator including a first input unit, a second input, and an output which is connected to the voltage converter; a reference voltage source supplying a reference voltage to the first input; a feedback feeding back a voltage divided by the resistor to the second input from a node between the first switch and the second switch; a setting voltage source, to the second input; a third switch connected between the setting voltage source and the second input; and a control signal generator controlling the first switch, the second switch, and the third switch.

摘要翻译： 本公开涉及一种电源电路，其包括接收外部电压并输出内部电压的电压转换器; 连接在电压转换器的输出端和恒定电压源之间的第一开关和第二开关; 设置在所述第一开关和所述第二开关之间并且分压所述内部电压的电阻器; 比较器，包括连接到电压转换器的第一输入单元，第二输入端和输出端; 将参考电压提供给所述第一输入端的参考电压源; 反馈器将来自第一开关和第二开关之间的节点的电阻分压到第二输入端; 一个设定电压源到第二个输入端; 连接在所述设定电压源和所述第二输入端之间的第三开关; 以及控制信号发生器，控制第一开关，第二开关和第三开关。

公开(公告)号：US07449937B2

公开(公告)日：2008-11-11

申请号：US11555390

申请日：2006-11-01

申请人： Yoshikazu Takeyama

发明人： Yoshikazu Takeyama

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： A power supply circuit, comprises a booster circuit that boosts the voltage supplied from a power supply to produce an output voltage; a voltage divider circuit that divides said output voltage by resistive division and outputs a monitored voltage; a comparator circuit that compares said monitored voltage with a reference voltage and outputs a signal to activate said booster circuit if said monitored voltage is lower than said reference voltage and a signal to deactivate said booster circuit if said monitored voltage is higher than said reference voltage; an auxiliary instruction circuit that outputs an auxiliary signal to control the timing of the activation of said booster circuit; and an arithmetic circuit that performs a calculation using said auxiliary signal and the output signal of said comparator circuit and outputs an enable signal to activate said booster circuit if the output signal of said comparator circuit is a signal to activate said booster circuit, or said auxiliary signal is a signal to activate said booster circuit.

摘要翻译： 电源电路包括升压电路，其升压从电源供应的电压以产生输出电压; 分压电路，通过电阻分压分压所述输出电压，并输出监控电压; 比较电路，其将所述监测电压与参考电压进行比较，并且如果所述监测电压低于所述参考电压，则输出信号以激活所述升压电路，以及如果所述监测电压高于所述参考电压则停止所述升压电路的信号; 辅助指令电路，其输出辅助信号以控制所述升压电路的启动的定时; 以及算术电路，其使用所述辅助信号和所述比较器电路的输出信号进行计算，并且如果所述比较器电路的输出信号是激活所述升压电路的信号，则输出使能信号以激活所述升压电路，或所述辅助 信号是激活所述升压电路的信号。

公开(公告)号：US20080304349A1

公开(公告)日：2008-12-11

申请号：US12133701

申请日：2008-06-05

申请人： Toshihiro Suzuki ,  Yoshikazu Takeyama

发明人： Toshihiro Suzuki ,  Yoshikazu Takeyama

IPC分类号： G11C5/14 ,  G05F1/10

CPC分类号： G11C5/145 ,  G11C16/0483 ,  G11C16/12 ,  H02M3/073 ,  H02M2003/075

摘要： A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit.

摘要翻译： 从输出端子切换并输出多个设定电压的电压供给电路具有升压电路，其升压从电源供给的电压，并将该电压输出到输出端子; 电压检测电路，当检测到从升压电路输出的电压不低于设定电压时，输出第一标志信号，当检测到从升压电路输出的电压不低于频率调整电压时，输出第二标志 设定低于设定电压; 以及控制电路，其根据设定电压和电压检测电路的输出信号来控制升压电路的动作。

公开(公告)号：US20080137428A1

公开(公告)日：2008-06-12

申请号：US11939984

申请日：2007-11-14

申请人： Jun Nakai ,  Yoshikazu Takeyama

发明人： Jun Nakai ,  Yoshikazu Takeyama

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/14

摘要： A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

摘要翻译： 电源电路响应于控制信号输出不同的设定电位，其中电压检测电路响应于控制信号的输入而改变第一参考电位和第二参考电位的电平，并且时钟产生电路增加频率的频率 当第一参考电位和第二参考电位的电平响应于控制信号的输入而大大改变时的分频时钟信号。

公开(公告)号：US20140146607A1

公开(公告)日：2014-05-29

申请号：US13985436

申请日：2012-02-17

申请人： Yuji Nagai ,  Atsushi Inoue ,  Yoshikazu Takeyama

发明人： Yuji Nagai ,  Atsushi Inoue ,  Yoshikazu Takeyama

IPC分类号： G11C16/22

CPC分类号： G11C16/22 ,  G06F7/58 ,  G06F7/584

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.

摘要翻译： 根据一个实施例，半导体存储器件包括包括多个存储器单元的存储单元阵列，被配置为产生随机数的随机数生成电路以及配置为控制存储单元阵列和随机数产生电路的控制器。 随机数生成电路包括：随机数控制电路，被配置为基于通过生成的控制参数从存储器单元读出的数据生成随机数参数;以及伪随机数生成电路，被配置为通过 使用随机数参数作为种子值。