公开(公告)号：US5072271A

公开(公告)日：1991-12-10

申请号：US563120

申请日：1990-08-06

申请人： Mitsuru Shimizu ,  Yoshio Okada ,  Kiyofumi Sakurai

发明人： Mitsuru Shimizu ,  Yoshio Okada ,  Kiyofumi Sakurai

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H02H9/02

CPC分类号： H01L27/0259

摘要： A protection circuit is inserted between a signal input pad and an internal circuit. The protection circuit includes a parasitic bipolar transistor which is obtained by forming high-impurity concentration semiconductor regions in the major-surface region of a substrate. In practice, it is hard to provide a parasitic bipolar transistor of a sufficiently large size, since the reduction of the size of a chip is a recent trend. With this in mind, a third semiconductor region serving as an electron-trapping region is formed in a region outside of the location where the parasitic bipolar transistor is formed. If an excessive voltage produced by ESD or the like is applied to the pad, and the excessive voltage uncontrollable by the parasitic bipolar transistor, the third semiconductor region absorbs the excessive voltage. In particular, where the current capacity of the parasitic bipolar transistor is small, the third semiconductor region reliably prevents electrostatic destruction of a circuit element. Accordingly, the protection circuit enables the parasitic bipolar transistor to be reduced in size, thus contributing to miniaturization of a chip. Moreover, the protection circuit is reliable in operation.

公开(公告)号：US5066997A

公开(公告)日：1991-11-19

申请号：US436646

申请日：1989-11-15

申请人： Kiyofumi Sakurai ,  Syuso Fujii ,  Mitsuru Shimizu

发明人： Kiyofumi Sakurai ,  Syuso Fujii ,  Mitsuru Shimizu

IPC分类号： H01L21/3205 ,  G11C5/06 ,  G11C11/401 ,  H01L21/822 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/5283 ,  G11C5/063 ,  H01L27/108 ,  H01L2924/0002

摘要： A semiconductor device comprises a semiconductor chip and a memory array constituted by a plurality of memory blocks formed in the semiconductor chip and each having the essentially same construction and a plurality of bit lines arranged in columns at a predetermined interval. The semiconductor device further comprises a dummy wiring pattern arranged ajacent to the memory array in the semiconductor chip and including a dummy wiring layer set apart from outermost bit lines of each memory block a distance equal to the predetermined interval.

公开(公告)号：US6104233A

公开(公告)日：2000-08-15

申请号：US180770

申请日：1994-01-10

申请人： Syuso Fujii ,  Mitsuru Shimizu ,  Kiyofumi Sakurai

发明人： Syuso Fujii ,  Mitsuru Shimizu ,  Kiyofumi Sakurai

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L25/00

CPC分类号： H01L27/1104 ,  H01L27/0248

摘要： A p-well region (16) is formed in the main surface area of an n-type semiconductor substrate (11). A potential (V.sub.BB) which is lower than an externally input potential is applied to the p-well region (16). In the surface area of the p-well region (16), a first impurity diffused layer (12) of n-type to which the externally input potential (Vin) is applied and a second impurity diffused layer (13) of n-type to which a reference potential is applied are formed. The first impurity diffused layer (12) serves as the drain region of a first MOS transistor (Q9) of n-channel formed in the p-well region (16) and the second impurity diffused layer (13) serves as the drain region of a second MOS transistor (Q10) of n-channel which is also formed in the p-well region (16). The first and second MOS transistors (Q9 and Q10) constitute the input section of an input circuit. The input circuit detects the level of the externally input potential (Vin) by comparing the externally input potential (Vin) with the reference potential (Vref).

摘要翻译： 在n型半导体衬底（11）的主表面区域中形成p阱区（16）。 低于外部输入电位的电位（VBB）被施加到p阱区域（16）。 在p阱区域（16）的表面区域中，施加有外部输入电位（Vin）的n型第一杂质扩散层（12）和n型第二杂质扩散层（13） 形成施加基准电位的电位。 第一杂质扩散层（12）用作在p阱区域（16）中形成的n沟道的第一MOS晶体管（Q9）的漏极区域，并且第二杂质扩散层（13）用作漏极区域 还形成在p阱区域（16）中的n沟道的第二MOS晶体管（Q10）。 第一和第二MOS晶体管（Q9和Q10）构成输入电路的输入部分。 输入电路通过将外部输入电位（Vin）与参考电位（Vref）进行比较来检测外部输入电位（Vin）的电平。

公开(公告)号：US08233325B2

公开(公告)日：2012-07-31

申请号：US13108641

申请日：2011-05-16

申请人： Kiyofumi Sakurai ,  Takuya Futatsuyama

发明人： Kiyofumi Sakurai ,  Takuya Futatsuyama

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.

摘要翻译： 一种利用存储块控制闪速存储器编程的方法。 该方法包括检查存储器块中的所选块是否属于第一组或第二组。 该方法还包括当所选择的块属于第一组时从最小位地址执行编程。 该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。

公开(公告)号：US07650584B2

公开(公告)日：2010-01-19

申请号：US11838605

申请日：2007-08-14

申请人： Hitoshi Shiga ,  Kiyofumi Sakurai ,  Kenji Mima

发明人： Hitoshi Shiga ,  Kiyofumi Sakurai ,  Kenji Mima

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5077 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/11898

摘要： An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

摘要翻译： ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是 连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线， 并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心， 电线从二线以上。

公开(公告)号：USRE37427E1

公开(公告)日：2001-10-30

申请号：US09493001

申请日：2000-01-27

申请人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

发明人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

IPC分类号： G11C1300

CPC分类号： G11C7/1012 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1006 ,  G11C11/4093 ,  G11C11/4096

摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

摘要翻译： 在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。 每个子阵列设置有与字线并行形成的数据线。 数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。 这种布置允许数据路径被缩短并且能够高速传送数据。

公开(公告)号：US5642326A

公开(公告)日：1997-06-24

申请号：US534558

申请日：1995-09-27

申请人： Kiyofumi Sakurai ,  Satoru Takase ,  Masaki Ogihara

发明人： Kiyofumi Sakurai ,  Satoru Takase ,  Masaki Ogihara

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C8/18

摘要： A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.

摘要翻译： 动态存储器包括控制电路，用于根据外部提供给它的+ E，ovs RAS + EE信号和用于控制选定字线的字线控制电路来控制行解码器的选择和感测放大器的激活 将连接到各个存储器单元的位线上连接到字线的存储单元读出的电位在由该位线对应的读出放大器在 从+ E，ovs RAS + EE信号变为有效电平的时间段和其回到无效电平的时间。 具有栅极氧化膜的动态存储器被设计为经受较少的电场强度以便最小化可靠性的劣化，并且存储器可以有效地减少字线驱动升压电压的下降以消除泄漏的必要性 电流补偿电路。 此外，存储器减少了恢复数据读取操作的电位所需的时间以及数据写入操作所需的周期时间。

公开(公告)号：US20080074929A1

公开(公告)日：2008-03-27

申请号：US11838605

申请日：2007-08-14

申请人： Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

发明人： Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

IPC分类号： G11C11/34 ,  G06F17/50 ,  H01L23/52

CPC分类号： G06F17/5077 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/11898

摘要： An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

摘要翻译： ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是 连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线， 并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心， 电线从二线以上。

公开(公告)号：US5410512A

公开(公告)日：1995-04-25

申请号：US64438

申请日：1993-05-21

申请人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

发明人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C7/1021

摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

摘要翻译： 半导体存储器件包括形成在芯片中的硅芯片和子阵列。 在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。 此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。 连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

公开(公告)号：US07952930B2

公开(公告)日：2011-05-31

申请号：US12497153

申请日：2009-07-02

申请人： Kiyofumi Sakurai ,  Takuya Futatsuyama

发明人： Kiyofumi Sakurai ,  Takuya Futatsuyama

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory according to examples of the invention includes a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction and first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array. An address allocation to the word lines in the first NAND block is inverted against an address allocation to the word lines in the third NAND block.

摘要翻译： 根据本发明的示例的NAND闪速存储器包括由在第一方向依次布置的第一，第二和第NAND NAND块和第一和第二转移晶体管块组成的存储单元阵列，第一和第二转移晶体管块在第一方向依次排列， 与存储单元阵列的第一方向相交的第二方向。 对第一NAND块中的字线的地址分配与第三NAND块中的字线的地址分配相反。