公开(公告)号：US5532963A

公开(公告)日：1996-07-02

申请号：US523741

申请日：1995-09-05

申请人： Natsuki Kushiyama ,  Tohru Furuyama ,  Kenji Numata

发明人： Natsuki Kushiyama ,  Tohru Furuyama ,  Kenji Numata

IPC分类号： G11C29/02 ,  G11C29/24 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

摘要翻译： 半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟 通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线， 线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据 的存储单元阵列到相关位线上。

公开(公告)号：US5428576A

公开(公告)日：1995-06-27

申请号：US325636

申请日：1994-10-19

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C29/00 ,  G11C29/06 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4085 ,  G11C29/46 ,  G11C29/50 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401

摘要： A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.

摘要翻译： 一种包括多个电路块的半导体器件，其中分配了包括至少一个升高或降低的电位的各种电位。 该装置还包括用于选择性地和反向地改变分配给电路块的电位的装置。

公开(公告)号：US5343087A

公开(公告)日：1994-08-30

申请号：US713014

申请日：1991-06-10

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C11/408 ,  G05F3/20 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H03K3/01

CPC分类号： G05F3/205

摘要： A semiconductor device includes an enhancement MOS transistor formed in a semiconductor substrate and a substrate bias generator supplies a predetermined bias voltage to the substrate. The impurity concentration of the substrate is within the range in which the enhancement MOS transistor keeps the enhancement mode when the substrate potential equals to the built-in potential .PHI.B.

摘要翻译： 半导体器件包括形成在半导体衬底中的增强型MOS晶体管，衬底偏置发生器向衬底提供预定的偏置电压。 当衬底电位等于内置电位PHI B时，衬底的杂质浓度在增强MOS晶体管保持增强模式的范围内。

公开(公告)号：US5287312A

公开(公告)日：1994-02-15

申请号：US813492

申请日：1991-12-26

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4087 ,  G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

摘要翻译： 根据本发明的动态随机存取存储器包括以行和列排列的多个动态存储器单元，连接到同一行上的存储器单元的字线，连接到同一列上的存储器单元的位线， 字线选择电路，具有响应于内部地址信号选择任意一行的字线选择功能，字线驱动电压源，字线驱动电路，具有连接在字线之间的至少一个驱动MOS晶体管 驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号来控制字线驱动 使得字线驱动电路在接收到外部地址信号时比在正常操作模式中选择的字线更多地驱动字线。

公开(公告)号：US5276647A

公开(公告)日：1994-01-04

申请号：US813438

申请日：1991-12-26

申请人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

IPC分类号： G11C11/413 ,  G01R31/28 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C8/12 ,  G11C11/41

摘要： SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

摘要翻译： SRAM包括字线驱动电路，其根据正常操作时的输入地址选择预定数量的字线，并且同时选择大于所选择的字线数量的所有字线或字线 在正常工作时，在电压应力测试时，以及在正常工作时向所述一对位线施加预定偏置电压的位线负载电路，并且将偏置电压控制为不 施加到所述一对位线中的至少一个或在电压应力测试时施加低于正常操作时的偏置电压的偏置电压。

公开(公告)号：US5148393A

公开(公告)日：1992-09-15

申请号：US375909

申请日：1989-07-06

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： H01L27/04 ,  G11C11/404 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/404 ,  H01L27/10805

摘要： A semiconductor memory according to the present invention comprises a MOS dynamic semiconductor memory cell in which one terminal of a current path of one MOS transistor is connected to one capacitor element, the other terminal of the current path of the MOS transistor is connected to a bit line, and a gate electrode of the transistor is connected to a word line, wherein a substrate of the MOS transistor is not connected to a fixed potential terminal, and the potential of the substrate is switched and controlled so that the MOS transistor time-selectively becomes an enhancement type or a depletion type which can prevent a threshold voltage loss over time.

公开(公告)号：US5014245A

公开(公告)日：1991-05-07

申请号：US540770

申请日：1990-06-20

申请人： Kazuyoshi Muroka ,  Takashi Ohsawa ,  Tohru Furuyama

发明人： Kazuyoshi Muroka ,  Takashi Ohsawa ,  Tohru Furuyama

IPC分类号： G11C11/409 ,  G11C11/4076 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/4076

摘要： A dynamic random access memory includes switching transistors connected between bit lines and a sensing amplifier. The switching transistors are made non-conductive during a first period. An internal write enable signal is supplied for a predetermined period to a data input circuit to write a data into a memory cell of the dynamic random access memory. The predetermined period is controlled to terminate after the termination of the first period at an early write mode.

摘要翻译： 动态随机存取存储器包括连接在位线和感测放大器之间的开关晶体管。 开关晶体管在第一周期内被制成不导电的。 向数据输入电路提供预定时间段的内部写使能信号，以将数据写入到动态随机存取存储器的存储单元中。 控制预定周期以在早期写入模式下在第一周期结束之后终止。

公开(公告)号：US4697252A

公开(公告)日：1987-09-29

申请号：US587975

申请日：1984-03-09

申请人： Tohru Furuyama ,  Yukimasa Uchida

发明人： Tohru Furuyama ,  Yukimasa Uchida

IPC分类号： G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4074 ,  G11C11/4087

摘要： A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer, at least one memory cell having a capacitor for storing charges of an amount corresponding to a logic value and a first transistor having source and drain regions formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor, a first drive circuit for applying a voltage to the gate of the first transistor through a word line, a second drive circuit for selectively applying a voltage of one of first and second levels through a bit line and the first transistor to the capacitor, and a bias circuit for applying a voltage to the substrate. The first transistor of the memory device is a p-channel transistor formed in the n-type semiconductor layer which is formed in the surface area of a p-type semiconductor layer. The bias circuit includes a charge pump section for setting the potential of the substrate at a third level lower than the first voltage.

摘要翻译： 公开了一种动态型半导体存储器件，其包括n型半导体层，至少一个存储单元，具有用于存储对应于逻辑值的量的电荷的电容器和具有形成在该表面中的源极和漏极区域的第一晶体管 p型半导体层的区域和用于将电荷转移到电容器的第一驱动电路，用于通过字线向第一晶体管的栅极施加电压的第一驱动电路，用于选择性地施加电压的第二驱动电路， 通过位线和第一晶体管到电容器的第一和第二电平，以及用于向基板施加电压的偏置电路。 存储器件的第一晶体管是形成在p型半导体层的表面区域中的n型半导体层中形成的p沟道晶体管。 偏置电路包括用于将衬底的电位设置在低于第一电压的第三电平的电荷泵部分。

公开(公告)号：US5890186A

公开(公告)日：1999-03-30

申请号：US895863

申请日：1997-07-17

申请人： Katsuhiko Sato ,  Shinji Miyano ,  Tomoaki Yabe ,  Tohru Furuyama

发明人： Katsuhiko Sato ,  Shinji Miyano ,  Tomoaki Yabe ,  Tohru Furuyama

IPC分类号： G11C11/409 ,  G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/34

CPC分类号： G11C7/1051 ,  G11C11/005

摘要： When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

摘要翻译： 当存储在存储单元阵列的存储单元中的数据被写入高速缓冲存储器时，写入信号LW被设置为“H”电平。 写入信号LW通过初始化控制电路输入到数据线对初始化选择电路，信号EQE在所有列中被设置为“H”电平。 然后，数据线对初始化电路将所有列中的数据线对的电位设置在相同的电平。 当写信号LW通过传输门控制电路输入到传输门时，所有列中的传输门被接通。 传输门控制电路的延迟时间与初始化控制的延迟时间相同或更大。

公开(公告)号：US5673229A

公开(公告)日：1997-09-30

申请号：US612759

申请日：1996-03-08

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4087 ,  G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

摘要翻译： 动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线 晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。 此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号 线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管 其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。