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    Level shifter having automatic delay adjusting function
    1.
    发明授权
    Level shifter having automatic delay adjusting function 有权
    电平移位器具有自动延时调整功能

    公开(公告)号：US07148735B2

    公开(公告)日：2006-12-12

    申请号：US11191009

    申请日：2005-07-28

    申请人： Miwa Ito ,  Kazuyuki Nakanishi ,  Akio Hirata ,  Hiroo Yamamoto ,  Tsuguyasu Hatsuda

    发明人： Miwa Ito ,  Kazuyuki Nakanishi ,  Akio Hirata ,  Hiroo Yamamoto ,  Tsuguyasu Hatsuda

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113 ,  H03K3/011

    摘要： In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.

    摘要翻译： 在电平移位器中，输入到输入端子的输入信号（即，第一电源电压VDDL）的振幅电压变化为较高，输出信号的振幅电压（即，第二电源电压 从输出端子输出的VDDH）变低，从输出端子输出的信号的下降延迟时间趋于长于信号的上升延迟时间。 然而，由逆变器获得的反相输入信号被输入到电平移位单元，并输入到N型晶体管的栅极，因此，在输入信号的输入信号的下降时，N型晶体管导通 输入端子，以便将基于第二电源电压VDDH的电流提供给电平移位单元的输出节点，用于辅助在电平转换单元中执行的向H电平的移位。 因此，即使当输入信号的振幅电压和输出信号的振幅电压中的至少一个改变时，也能够令人满意地保持输出信号的下降延迟时间特性和上升延迟时间特性之间的平衡。

    Level shifter having automatic delay adjusting function
    2.
    发明申请
    Level shifter having automatic delay adjusting function 有权
    电平移位器具有自动延时调整功能

    公开(公告)号：US20050258887A1

    公开(公告)日：2005-11-24

    申请号：US11191009

    申请日：2005-07-28

    申请人： Miwa Ito ,  Kazuyuki Nakanishi ,  Akio Hirata ,  Hiroo Yamamoto ,  Tsuguyasu Hatsuda

    发明人： Miwa Ito ,  Kazuyuki Nakanishi ,  Akio Hirata ,  Hiroo Yamamoto ,  Tsuguyasu Hatsuda

    IPC分类号： H03K19/0185 ,  H03K3/011 ,  H03K3/356 ,  H03K5/153 ,  H03L5/00

    CPC分类号： H03K3/356113 ,  H03K3/011

    摘要： In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.

    摘要翻译： 在电平移位器中，输入到输入端子的输入信号（即，第一电源电压VDDL）的振幅电压变化为较高，输出信号的振幅电压（即，第二电源电压 从输出端子输出的VDDH）变低，从输出端子输出的信号的下降延迟时间趋于长于信号的上升延迟时间。 然而，由逆变器获得的反相输入信号被输入到电平移位单元，并输入到N型晶体管的栅极，因此，在输入信号的输入信号的下降时，N型晶体管导通 输入端子，以便将基于第二电源电压VDDH的电流提供给电平移位单元的输出节点，用于辅助在电平转换单元中执行的向H电平的移位。 因此，即使当输入信号的振幅电压和输出信号的振幅电压中的至少一个改变时，也能够令人满意地保持输出信号的下降延迟时间特性和上升延迟时间特性之间的平衡。

    Flip-flop circuit
    3.
    发明授权
    Flip-flop circuit 有权
    触发电路

    公开(公告)号：US06853228B2

    公开(公告)日：2005-02-08

    申请号：US10686597

    申请日：2003-10-17

    申请人： Akio Hirata ,  Masahiro Gion ,  Kazuyuki Nakanishi

    发明人： Akio Hirata ,  Masahiro Gion ,  Kazuyuki Nakanishi

    IPC分类号： H03K3/012 ,  H03K3/037

    CPC分类号： H03K3/012 ,  H03K3/037

    摘要： In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit INV1 constituting a latch circuit 2 connected to the output terminal of an input section 1 is used as an input signal of a control section 3. Thus, a control signal output from the control section 3 to the input section 1 is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section 3 is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

    摘要翻译： 在包括使用动态电路的输入部分和使用静态电路的输出部分并且在短于时钟周期的脉冲宽度的周期内捕获数据的触发器电路中，晶体管数量，电路面积和功率消耗 减少了 在图 如图1所示，构成与输入部1的输出端子连接的锁存电路2的反相器电路INV1的输出信号被用作控制部分3的输入信号。因此，从控制部分3输出到控制部分3的控制信号 输入部分1稳定，从而抑制电路元件的不必要的操作并减少不必要的功耗。 另外，简化了控制部3的结构。 结果，可以减少构成电路的晶体管的数量和电路面积。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08431967B2

    公开(公告)日：2013-04-30

    申请号：US13020566

    申请日：2011-02-03

    申请人： Kazuyuki Nakanishi ,  Masaki Tamaru

    发明人： Kazuyuki Nakanishi ,  Masaki Tamaru

    IPC分类号： H01L27/118

    CPC分类号： H01L27/0207

    摘要： A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

    摘要翻译： 半导体器件的布局能够可靠地降低由于光学邻近效应引起的栅极长度的变化，并且能够实现灵活的布局设计。 单元（C1）的栅极图案（G1，G2，G3）以相同的间距排列，并且栅极图案的末端（e1，e2，e3）位于与Y方向相同的位置， 相同宽度的X方向。 电池（C2）的栅极图案（G4）具有在Y方向朝向电池单元（C1）突出的突出部分（4b），并且突出部分（4b）形成相对的末端（eo1，eo2，eo3）。 相对的末端（eo1，eo2，eo3）以与栅极图案（G1，G2，G3）相同的间距配置在与Y方向相同的位置，并且在X方向上具有相同的宽度。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    6.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20080224176A1

    公开(公告)日：2008-09-18

    申请号：US12048837

    申请日：2008-03-14

    申请人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

    发明人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

    IPC分类号： H01L27/10

    CPC分类号： H01L27/0203 ,  H01L27/11807

    摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

    摘要翻译： 提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。 在垂直方向上延伸的包括栅极G的多个标准单元（C 1，C 2，C 3，...）在横向方向上排列以形成标准单元行。 多个标准单元行在垂直方向上并排设置以形成标准单元组。 每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。 终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

    Semiconductor device and layout design method for the same
    7.
    发明申请
    Semiconductor device and layout design method for the same 有权
    半导体器件和布局设计方法相同

    公开(公告)号：US20060181309A1

    公开(公告)日：2006-08-17

    申请号：US11354936

    申请日：2006-02-16

    申请人： Kazuyuki Nakanishi

    发明人： Kazuyuki Nakanishi

    IPC分类号： H03K19/177

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： A rectangular opening is formed in a power supply line which is shared between cell rows. A connection to a substrate potential supply line is ensured in the rectangular opening.

    摘要翻译： 在单元列之间共享的电源线中形成矩形开口。 在矩形开口中确保与衬底电位供给线的连接。

    Method of forming a nitride or carbonitride layer
    8.
    发明授权
    Method of forming a nitride or carbonitride layer 失效
    形成氮化物或碳氮化物层的方法

    公开(公告)号：US5443662A

    公开(公告)日：1995-08-22

    申请号：US84322

    申请日：1993-06-30

    申请人： Tohru Arai ,  Kazuyuki Nakanishi ,  Hiromasa Takeda ,  Hideo Tachikawa

    发明人： Tohru Arai ,  Kazuyuki Nakanishi ,  Hiromasa Takeda ,  Hideo Tachikawa

    IPC分类号： C23C8/06 ,  C23C8/24 ,  C23C8/30 ,  C23C16/442 ,  C23C16/44 ,  B05D1/22

    CPC分类号： C23C16/442

    摘要： A nitride or carbonitride layer is formed on the surface of a metal material as follows: A treating agent composed of a refractory powder of alumina or the like and a powder of a metal for forming a nitride or a carbide or an alloy thereof is disposed in a fluidized bed furnace; the treating agent is fluidized to form a fluidized bed by introducing an inert gas; the fluidized bed furnace is heated to a temperature of not higher than 700.degree. C.; an activator of a halogenated ammonium salt is intermittently supplied into the fluidized bed at a rate of 0.001 to 5 wt %/hour based on the total amount of the treating agent; and the metal material to be treated is disposed in the fluidized bed during or after any of the above steps. For example, a nitride layer composed of only a metal for forming a nitride which contains almost no Fe--N is formed on the surface of iron steel even at a temperature as low as not higher than 700.degree. C. The layer is very hard and efficient in wear resistance, and the toughness of the base metal is hardly lowered.

    摘要翻译： 在金属材料的表面上如下形成氮化物或碳氮化物层：由氧化铝等的耐火材料粉末和用于形成氮化物的金属粉末或其合金构成的处理剂设置在 流化床炉; 通过引入惰性气体使处理剂流化形成流化床; 将流化床炉加热至不高于700℃的温度; 基于处理剂的总量，以0.001至5重量％/小时的速率将卤化铵盐的活化剂间歇地供给到流化床中; 并且在任何上述步骤期间或之后将要处理的金属材料设置在流化床中。 例如，即使在700℃以下的温度下，也在铁钢的表面上形成仅由形成几乎不含Fe-N的氮化物的金属构成的氮化物层。该层非常硬， 耐磨损性高，贱金属的韧性几乎不降低。

    Method and apparatus for forming film
    9.
    发明授权
    Method and apparatus for forming film 有权
    薄膜成膜方法及装置

    公开(公告)号：US08652587B2

    公开(公告)日：2014-02-18

    申请号：US13046208

    申请日：2011-03-11

    申请人： Kazuyuki Nakanishi ,  Takashi Iseki ,  Yasuhiro Ozawa ,  Yuka Yamada ,  Seiji Mizuno ,  Katsumi Sato ,  Masafumi Koizumi ,  Yoshiyuki Funaki ,  Kyouji Kondo ,  Takayuki Kikuchi

    发明人： Kazuyuki Nakanishi ,  Takashi Iseki ,  Yasuhiro Ozawa ,  Yuka Yamada ,  Seiji Mizuno ,  Katsumi Sato ,  Masafumi Koizumi ,  Yoshiyuki Funaki ,  Kyouji Kondo ,  Takayuki Kikuchi

    IPC分类号： H05H1/24

    CPC分类号： C23C16/26 ,  C23C16/503 ,  C23C16/545

    摘要： This invention adopts plasma-enhanced chemical vapor deposition using the apparatus including a chamber, a pair of rotary electrode reels including a feed-out reel and a take-up reel, a plasma source, a material gas supplier, and an exhaust unit, and includes applying a negative voltage applied to the rotary electrode reels from the plasma source while a conductive substrate is fed-out from the feed-out reel and is wound on the take-up reel so that the entire surface of the substrate portion between reels contacts the material gas, whereby plasma sheath is formed along the surface of the substrate portion between reels, and the material gas is activated in the plasma sheath and thus contacts the surface of the substrate, thus forming the film on the surface of the substrate.

    摘要翻译： 本发明采用等离子体增强化学气相沉积法，该装置包括一个室，一对旋转电极卷轴，包括一个送出卷轴和一个卷取卷轴，等离子体源，原料气体供应器和排气单元，以及 包括在从所述送出卷轴送出导电性基板并卷绕在所述卷取卷轴上时，施加从所述等离子体源施加到所述旋转电极卷轴上的负电压，使得所述基板部分在卷盘接触之间的整个表面 材料气体，由此在卷轴之间沿着基板部分的表面形成等离子体护套，并且材料气体在等离子体护套中被激活，并且因此接触基板的表面，从而在基板的表面上形成膜。