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公开(公告)号：US20230085673A1
公开(公告)日：2023-03-23
申请号：US17482056
申请日：2021-09-22
申请人： Mohamed A. Abdelmoneum , Eduardo Alban , Whitney Bryks , Brent R. Carlton , Tarek A. Ibrahim , Nasser A. Kurd , Jason Mix , Srinivas Venkata Ramanuja Pietambaram , Sarah Shahraini
发明人： Mohamed A. Abdelmoneum , Eduardo Alban , Whitney Bryks , Brent R. Carlton , Tarek A. Ibrahim , Nasser A. Kurd , Jason Mix , Srinivas Venkata Ramanuja Pietambaram , Sarah Shahraini
IPC分类号： H01L41/187 , H01L41/09 , H01L41/35 , B81B3/00 , H03H9/02
摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.
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公开(公告)号：US20230253976A1
公开(公告)日：2023-08-10
申请号：US17667786
申请日：2022-02-09
CPC分类号： H03M1/1023 , G04F10/005
摘要： An apparatus, system, and method for are provided. A device includes a time-to-digital converter (TDC) situated to convert a time-domain signal to a digital value, a delay circuit situated in parallel with the TDC and to delay the time-domain signal by a specified amount of time resulting in a delayed time-domain signal, a time-to-voltage converter (TVC) situated to produce a voltage-domain signal based on the delayed time-domain signal, and a successive approximation (SAR) circuit situated to receive the digital value and the voltage-domain signal and produce a digital-domain version of the input signal.
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3.发明申请公开(公告)号：US20090325529A1
公开(公告)日：2009-12-31
申请号：US12147365
申请日：2008-06-26
IPC分类号： H04B1/10
CPC分类号： H04B17/21
摘要： Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.
摘要翻译： 本文公开了用于校准接收链以减少二阶互调失真的装置，制品，方法和系统的实施例。 可以采用这些实施例，例如来管理无线网络中的功率。 可以描述和要求保护其他实施例和用法。
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4.发明授权公开(公告)号：US06943626B2
公开(公告)日：2005-09-13
申请号：US10741642
申请日：2003-12-19
申请人： Donald T. Comer , Brent R. Carlton
发明人： Donald T. Comer , Brent R. Carlton
CPC分类号： H03F3/45475 , H03F3/3432 , H03F3/50 , H03F2200/36 , H03G3/30
摘要： An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.
摘要翻译： 公开了一种用于提高固定增益放大器的增益精度和带宽的装置和方法，同时提供许多应用中所需的高带宽和性能。 具有相对精确增益的固定增益放大器在特定架构中连接在一起，以进一步增加任何独立运行的放大器的增益精度和带宽。 由于放大器的配置，各放大器的绝对增益误差基本上被消除，所以总电路的增益误差大大降低。 公开的架构在需要非常精确的增益的许多高速，高带宽的应用中是有用的，同时避免了使用反馈来实现增益稳定性的放大器引起的带宽的减少。
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公开(公告)号：US20230208430A1
公开(公告)日：2023-06-29
申请号：US17561457
申请日：2021-12-23
IPC分类号： H03M1/10
CPC分类号： H03M1/1019
摘要： An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.
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6.发明授权公开(公告)号：US08112055B2
公开(公告)日：2012-02-07
申请号：US12147365
申请日：2008-06-26
申请人： Xuebin Yang , Xu Zhang , Jingyi Ma , Stewart S. Taylor , Brent R. Carlton
发明人： Xuebin Yang , Xu Zhang , Jingyi Ma , Stewart S. Taylor , Brent R. Carlton
IPC分类号： H04B1/12
CPC分类号： H04B17/21
摘要： Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. In some embodiments, a reference sensing chain is used to generate reference second-order intermodulation distortion signals that may be used to adjust a calibration code. In some embodiments, a calibration code may be adjusted using one or more feedback loops of a baseband amplifier. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.
摘要翻译： 本文公开了用于校准接收链以减少二阶互调失真的装置，制品，方法和系统的实施例。 在一些实施例中，参考感测链用于产生可用于调整校准码的参考二阶互调失真信号。 在一些实施例中，可以使用基带放大器的一个或多个反馈回路来调整校准代码。 可以采用这些实施例，例如来管理无线网络中的功率。 可以描述和要求保护其他实施例和用法。
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公开(公告)号：US20240106452A1
公开(公告)日：2024-03-28
申请号：US17955186
申请日：2022-09-28
CPC分类号： H03M1/38 , H03M1/1245
摘要： A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.
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