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公开(公告)号：US07479597B1
公开(公告)日：2009-01-20
申请号：US11946165
申请日：2007-11-28
IPC分类号： H01B7/00
CPC分类号： H01B7/30 , H01B7/0009
摘要： A cable having an electrically conducting wire with a cross sectional shape defined by a simple closed curve having from three to eight concave portions separated by an equal number of convex portions. The simple closed curve has no point where the radius of curvature is less than one-sixth (⅙) of an overall radius of the wire and no point where adjacent curves or lines intersect at an angle. The alternating concave and convex portions of the cable's cross-sectional shape may have substantially the same curvature. The cross-sectional shape of the cable avoids sharp angles and fight curves.
摘要翻译： 一种具有导线的电缆，其横截面形状由简单的闭合曲线限定，具有由相等数量的凸部分开的三至八个凹部。 简单的闭合曲线没有点曲率半径小于线的总半径的六分之一（1/6），而相邻的曲线或线不是以一定角度相交的点。 电缆的横截面形状的交替的凹凸部分可以具有基本相同的曲率。 电缆的横截面形状避免了锐角和抗弯曲。
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公开(公告)号：US07461303B2
公开(公告)日：2008-12-02
申请号：US11690200
申请日：2007-03-23
申请人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
发明人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G11C5/147 , G11C29/021
摘要： A system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.
摘要翻译： 通过监视电压调节器模块（VRM）来改善存储器子系统中的现场替换单元（FRU）隔离的系统引起的内存错误。 比较器将来自VRM的输出电压与存储器进行比较。 如果比较器检测到超出额定阈值的VRM输出电压瞬变，则计数器增加1。 如果计数器超过计数阈值，则发布VRM错误。 如果在预定时间内出现内存故障，则VRM错误将VRM输出电压瞬变定位为存储器故障的可能原因。
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公开(公告)号：US06912670B2
公开(公告)日：2005-06-28
申请号：US10054017
申请日：2002-01-22
申请人： Bruce James Wilkie
发明人： Bruce James Wilkie
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0793
摘要： A system and method for handling processor internal errors in a data processing system. The data processing system typically includes a set of main microprocessors that have access to a common system memory via a system bus. The system may further include a service processor that is connected to at least one of the main processors. In addition, the system includes internal error handling hardware configured to log and process internal errors generated by one or more of the main processors. The internal error hardware may include error detection logic configured to receive internal error signals from the main processors. In response to receiving one or more IERR signals, the error detection logic is configured to assert and error detected signal that is received by error logging logic. The error logging logic is configured to update one or more error status register when the error detected signal is asserted. When the error logging logic has updated the status registers, is configured to assert an error logging complete signal that is received by processing control logic. The processor control logic is configured to assert one or more processor enable signals based on the state of the error status registers. In addition, upon completion of the error status update by the error logging logic, the status register is configured to assert an error status updated signal that ultimately produces a system reset. By incorporating error logging and handling into dedicated hardware tied directly to the processor internal error signals, the invention provides a low cost, low response latency mechanism for handling processor internal errors in high performance multiprocessor systems.
摘要翻译： 一种用于处理数据处理系统中处理器内部错误的系统和方法。 数据处理系统通常包括通过系统总线访问公共系统存储器的一组主要微处理器。 系统还可以包括连接到至少一个主处理器的服务处理器。 此外，该系统还包括内部错误处理硬件，配置为记录和处理一个或多个主要处理器产生的内部错误。 内部错误硬件可以包括配置成从主处理器接收内部错误信号的错误检测逻辑。 响应于接收到一个或多个IERR信号，错误检测逻辑被配置为由错误记录逻辑接收的断言和错误检测信号。 错误记录逻辑被配置为在发出错误检测信号时更新一个或多个错误状态寄存器。 当错误记录逻辑更新状态寄存器时，配置为断言由处理控制逻辑接收到的错误记录完成信号。 处理器控制逻辑被配置为基于错误状态寄存器的状态断言一个或多个处理器使能信号。 另外，在通过错误记录逻辑完成错误状态更新之后，状态寄存器被配置为断言最终产生系统复位的错误状态更新信号。 通过将错误记录和处理结合到与处理器内部错误信号直接相关的专用硬件中，本发明提供了用于处理高性能多处理器系统中的处理器内部错误的低成本，低响应延迟机制。
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公开(公告)号：US6020900A
公开(公告)日：2000-02-01
申请号：US833232
申请日：1997-04-14
CPC分类号： G09G5/393
摘要： One aspect of the invention relates to a method for synchronizing control signals with scaled digital video data. In one version of the invention, the method includes the steps of transferring digitized video data from a digitizer to a video scaler which stores the digitized video data to form pixel data and generates a pixel qualifier signal to indicate when pixel data is valid; storing the pixel data into a field memory in response to the pixel qualifier signal from the video scaler; storing control signal data in a control memory in response to the pixel qualifier signal, the control signal data being representative of control signals provided by the video scaler, such that a correspondence is created between the pixel data stored in the field memory and the control signal data stored in the control memory; and transferring the pixel data stored in the field memory and the control signal data stored in the control memory to a bus interface unit, the bus interface unit being coupled to a data bus of a host processor, such that the correspondence between the pixel data and the control signal data is maintained during the transfer.
摘要翻译： 本发明的一个方面涉及一种用缩放的数字视频数据同步控制信号的方法。 在本发明的一个方案中，该方法包括以下步骤：将数字化视频数据从数字转换器传送到存储数字化视频数据以形成像素数据的视频缩放器，并产生像素限定信号以指示何时像素数据有效; 响应于来自视频缩放器的像素限定符信号，将像素数据存储到场存储器中; 响应于像素限定信号将控制信号数据存储在控制存储器中，控制信号数据表示由视频缩放器提供的控制信号，使得在存储在场存储器中的像素数据和控制信号之间产生对应关系 存储在控制存储器中的数据; 以及将存储在所述现场存储器中的像素数据和存储在所述控制存储器中的控制信号数据传送到总线接口单元，所述总线接口单元耦合到主机处理器的数据总线，使得所述像素数据和 在传送期间保持控制信号数据。
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公开(公告)号：US08484398B2
公开(公告)日：2013-07-09
申请号：US11000318
申请日：2004-11-30
CPC分类号： G06F13/4027
摘要： A data processing assembly includes one or more hosts connected to one or more I/O Expansion Drawers. Assignment state information is stored on the Expansion Drawer to convey the assignment state of Expansion Drawer(s) resources to the hosts. The host retrieves the assignment state and, from it, determines, for each Expansion Buss cable connected to the host, the number of Expansion Cards in the Expansion Drawer to configure. A change in the number of Expansion Cards in the expansion apparatus may necessitate a change in the assignment state, which can be electronically accommodated (as opposed to a manual reconfiguration). Similarly, a failure of an Expansion Buss cable is addressed by electronically reassigning resources to another host or to the same host over a different Expansion Buss cable without the need for further manual intervention. The assembly is capable of verifying correct cable connection between a host and the Expansion Drawer.
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6.发明授权System for transferring pixel data from a digitizer to a host memory using scatter/gather DMA 失效使用分散/聚集DMA将像素数据从数字转换器传输到主机存储器的系统
公开(公告)号：US5943504A
公开(公告)日：1999-08-24
申请号：US833231
申请日：1997-04-14
CPC分类号： H04N7/24
摘要： One aspect of the invention relates to a method for synchronizing control signals with scaled digital video data. In one version of the invention, the method includes the steps of transferring digitized video data from a digitizer to a video scaler which stores the digitized video data to form pixel data and generates a pixel qualifier signal to indicate when pixel data is valid; storing the pixel data into a field memory in response to the pixel qualifier signal from the video scaler; storing control signal data in a control memory in response to the pixel qualifier signal, the control signal data being representative of control signals provided by the video scaler, such that a correspondence is created between the pixel data stored in the field memory and the control signal data stored in the control memory; and transferring the pixel data stored in the field memory and the control signal data stored in the control memory to a bus interface unit, the bus interface unit being coupled to a data bus of a host processor, such that the correspondence between the pixel data and the control signal data is maintained during the transfer.
摘要翻译： 本发明的一个方面涉及一种用缩放的数字视频数据同步控制信号的方法。 在本发明的一个方案中，该方法包括以下步骤：将数字化视频数据从数字转换器传送到存储数字化视频数据以形成像素数据的视频缩放器，并产生像素限定信号以指示何时像素数据有效; 响应于来自视频缩放器的像素限定符信号，将像素数据存储到场存储器中; 响应于像素限定信号将控制信号数据存储在控制存储器中，控制信号数据表示由视频缩放器提供的控制信号，使得在存储在场存储器中的像素数据和控制信号之间产生对应关系 存储在控制存储器中的数据; 以及将存储在所述现场存储器中的像素数据和存储在所述控制存储器中的控制信号数据传送到总线接口单元，所述总线接口单元耦合到主机处理器的数据总线，使得所述像素数据和 在传送期间保持控制信号数据。
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7.发明申请公开(公告)号：US20090234936A1
公开(公告)日：2009-09-17
申请号：US12048624
申请日：2008-03-14
IPC分类号： G06F15/177
CPC分类号： G06F13/4072 , H04L12/40032 , H05K7/1492
摘要： In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.
摘要翻译： 在一个实施例中，用于多刀片服务器系统的通信系统包括将管理模块与多服务器机箱中的多个服务器中的每一个互连的多点串行总线网络。 第一收发器子系统被配置用于通过串行总线网络在管理模块和第一频带内的每个服务器之间进行通信。 第二收发器子系统被配置为在高于第一频带的第二频带内在管理模块和服务器之间通过串行总线网络同时通信。 第一信号滤波子系统基本上从第一收发器子系统滤出第二频带中的信号。 第二信号滤波子系统基本上从第二收发器子系统滤除第一频带中的信号。
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公开(公告)号：US20090031168A1
公开(公告)日：2009-01-29
申请号：US12246748
申请日：2008-10-07
申请人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
发明人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
IPC分类号： G06F11/26
CPC分类号： G11C29/02 , G11C5/147 , G11C29/021
摘要： A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.
摘要翻译： 通过监控电压调节器模块（VRM）引起的内存错误，改善了存储器子系统中的现场替换单元（FRU）隔离的方法和系统。 比较器将来自VRM的输出电压与存储器进行比较。 如果比较器检测到超出额定阈值的VRM输出电压瞬变，则计数器增加1。 如果计数器超过计数阈值，则发布VRM错误。 如果在预定时间内出现内存故障，则VRM错误将VRM输出电压瞬变定位为存储器故障的可能原因。
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公开(公告)号：US07269764B2
公开(公告)日：2007-09-11
申请号：US10872099
申请日：2004-06-18
申请人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
发明人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G11C5/147 , G11C29/021
摘要： A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.
摘要翻译： 通过监控电压调节器模块（VRM）引起的内存错误，改善了存储器子系统中的现场替换单元（FRU）隔离的方法和系统。 比较器将来自VRM的输出电压与存储器进行比较。 如果比较器检测到超出额定阈值的VRM输出电压瞬变，则计数器增加1。 如果计数器超过计数阈值，则发布VRM错误。 如果在预定时间内出现内存故障，则VRM错误将VRM输出电压瞬变定位为存储器故障的可能原因。
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公开(公告)号：US5646368A
公开(公告)日：1997-07-08
申请号：US565373
申请日：1995-11-30
CPC分类号： H05K1/0228 , H05K1/0245 , H05K2201/097
摘要： A multi-layered printed circuit board having an integrated twisted pair conductor. In a preferred embodiment, the printed circuit board comprises two segmented conductor traces on a first and a second layer of the printed circuit board crisscrossing each other and a plurality of vias. The two segmented conductor traces on the first layer are connected to the two segmented conductor traces on the second layer through the vias. The twisted pair conductor may be shielded by adding a ground trace on either side of the conductor traces and a ground plane both above and below the conductor traces. The conductor traces may also be tuned to specific electrical characteristics by properly spacing the plurality of vias such that a specific number of turns per unit length are achieved. The continuous conductor traces may be further tuned by using a specific dielectric thickness as well as by designing the conductor traces to be of a specific dimension.
摘要翻译： 一种具有集成双绞线导体的多层印刷电路板。 在优选实施例中，印刷电路板包括彼此交叉的印刷电路板的第一和第二层上的两个分段导体迹线和多个通孔。 第一层上的两个分段导体迹线通过通孔连接到第二层上的两个分段导体迹线。 可以通过在导体迹线的任一侧添加接地迹线和导体迹线上方和下方的接地平面来屏蔽双绞线导体。 也可以通过适当地间隔多个通孔使导体迹线调谐到特定的电特性，从而实现每单位长度的特定数量的匝数。 可以通过使用特定介电厚度以及通过将导体迹线设计成具体尺寸来进一步调谐连续导体迹线。
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