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    Method and system for exclusive two-level caching in a chip-multiprocessor
    2.
    发明授权
    Method and system for exclusive two-level caching in a chip-multiprocessor 有权
    芯片多处理器专用二级缓存的方法和系统

    公开(公告)号：US06912624B2

    公开(公告)日：2005-06-28

    申请号：US10769824

    申请日：2004-02-02

    申请人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    发明人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0826 ,  G06F12/0811 ,  G06F2212/621

    摘要： To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.

    摘要翻译： 为了最大限度地有效利用片上高速缓存，提供了一种用于芯片多处理器中独占二级缓存的方法和系统。 根据本发明的独有的两级缓存涉及在二级缓存系统中放宽包含要求的方法，以便形成专用高速缓存层级。 此外，独占的两级缓存涉及在二级缓存系统的一级缓存中提供一级标签状态结构。 第一个标签状态结构具有状态信息。 专有的两级缓存还涉及在二级缓存系统的二级缓存中维护第一级标签状态结构的副本，并扩展第一标签状态结构的副本中的状态信息，但是 不在第一级标签状态结构本身，包括所有者指示。 专用的两级缓存进一步包括在第二级缓存中提供第二标签状态结构，使得在第一标签状态结构和第二标签状态结构的副本处的同时查找是可能的。 此外，独占的两级缓存涉及在单芯片多处理器的任何给定的生命周期将单个所有者与缓存线相关联。

    Method and system for exclusive two-level caching in a chip-multiprocessor
    3.
    发明授权
    Method and system for exclusive two-level caching in a chip-multiprocessor 有权

    公开(公告)号：US06725334B2

    公开(公告)日：2004-04-20

    申请号：US09877530

    申请日：2001-06-08

    申请人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    发明人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    IPC分类号： G06F1200

    CPC分类号： G06F12/0826 ,  G06F12/0811 ,  G06F2212/621

    摘要： To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.

    Load control in a data center
    4.
    发明授权
    Load control in a data center 有权
    在数据中心进行负载控制

    公开(公告)号：US08700929B1

    公开(公告)日：2014-04-15

    申请号：US12134611

    申请日：2008-06-06

    申请人： Wolf-Dietrich Weber ,  Xiaobo Fan ,  Luiz Andre Barroso

    发明人： Wolf-Dietrich Weber ,  Xiaobo Fan ,  Luiz Andre Barroso

    IPC分类号： G06F1/00

    CPC分类号： G06F17/5009 ,  G06F1/00 ,  G06F1/3206 ,  G06F9/5094 ,  Y02D10/22

    摘要： A method of controlling power usage in a data center includes monitoring a power usage of a plurality of computers in the data center, generating a signal indicating that the power usage is within a threshold of a maximum power capacity, and in response to the signal, adjusting performance of at least one computer in the plurality of computers.

    摘要翻译： 一种控制数据中心的电力使用的方法包括监视数据中心中的多台计算机的电力使用情况，产生指示电力使用量在最大功率容量的阈值内的信号，并且响应于该信号， 调整所述多个计算机中的至少一台计算机的性能。

    Powering a data center
    8.
    发明授权
    Powering a data center 有权
    为数据中心供电

    公开(公告)号：US08595515B1

    公开(公告)日：2013-11-26

    申请号：US12134971

    申请日：2008-06-06

    申请人： Wolf-Dietrich Weber ,  Xiaobo Fan ,  Luiz Andre Barroso

    发明人： Wolf-Dietrich Weber ,  Xiaobo Fan ,  Luiz Andre Barroso

    IPC分类号： G06F1/00 ,  G06F1/32

    CPC分类号： G06F17/5009 ,  G06F1/00 ,  G06F1/3206 ,  G06F9/5094 ,  Y02D10/22

    摘要： A data center includes a power distribution network having a power capacity, and a plurality of computers drawing power from the power distribution network. Each of the computers has a peak power draw. The power capacity is less than a maximum power draw defined by summing the peak power draw from each of the plurality of computers.

    摘要翻译： 数据中心包括具有电力容量的配电网络和从配电网络抽取电力的多个计算机。 每个计算机都具有峰值功率。 功率容量小于通过将来自多个计算机中的每一个的峰值功率消耗相加而定义的最大功率消耗。

    Scalable architecture based on single-chip multiprocessing
    9.
    发明授权
    Scalable architecture based on single-chip multiprocessing 有权

    公开(公告)号：US06668308B2

    公开(公告)日：2003-12-23

    申请号：US09877793

    申请日：2001-06-08

    申请人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    发明人： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    IPC分类号： G06F1200

    CPC分类号： G06F12/0811 ,  G06F12/0826 ,  G06F2212/621

    摘要： A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRANHA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.