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1.发明授权Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance 有权通过适应线路电阻的温度依赖性在半导体中形成金属线的技术公开(公告)号：US08058731B2
公开(公告)日：2011-11-15
申请号：US11952522
申请日：2007-12-07
CPC分类号： H01L21/76877 , H01L21/76834 , H01L21/76864 , H01L21/76883 , Y10T428/31678
摘要： By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
摘要翻译： 通过适当地将缺陷引入诸如铜的高导电材料中，可以显着地修改电阻对温度行为，从而可以在先进的半导体器件的金属化结构中获得增强的电迁移行为和/或电性能。 电阻的缺陷相关部分可以适度增加，以便改变电阻对温度曲线的斜率，从而允许引入杂质原子以增强电迁移耐力，同时不会不适当地增加在工作温度下的整体电阻甚至甚至 降低在指定工作温度下的相应电阻。 因此，通过适当地设计目标工作温度的电阻，可以提高电迁移行为和电性能。
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2.发明授权Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance 有权通过适应线路电阻的温度依赖性在半导体中形成金属线的技术公开(公告)号：US08575029B2
公开(公告)日：2013-11-05
申请号：US13272876
申请日：2011-10-13
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76834 , H01L21/76864 , H01L21/76883 , Y10T428/31678
摘要： By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
摘要翻译： 通过适当地将缺陷引入诸如铜的高导电材料中，可以显着地修改电阻对温度行为，从而可以在先进的半导体器件的金属化结构中获得增强的电迁移行为和/或电性能。 电阻的缺陷相关部分可以适度增加，以便改变电阻对温度曲线的斜率，从而允许引入杂质原子以增强电迁移耐力，同时不会不适当地增加在工作温度下的整体电阻甚至甚至 降低在指定工作温度下的相应电阻。 因此，通过适当地设计目标工作温度的电阻，可以提高电迁移行为和电性能。
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3.发明申请TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE 有权通过适应线路电阻的温度依赖性在半导体中形成金属线的技术公开(公告)号：US20120088365A1
公开(公告)日：2012-04-12
申请号：US13272876
申请日：2011-10-13
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76834 , H01L21/76864 , H01L21/76883 , Y10T428/31678
摘要： By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
摘要翻译： 通过适当地将缺陷引入诸如铜的高导电材料中，可以显着地修改电阻对温度行为，从而可以在先进的半导体器件的金属化结构中获得增强的电迁移行为和/或电性能。 电阻的缺陷相关部分可以适度增加，以便改变电阻对温度曲线的斜率，从而允许引入杂质原子以增强电迁移耐力，同时不会不适当地增加在工作温度下的整体电阻甚至甚至 降低在指定工作温度下的相应电阻。 因此，通过适当地设计目标工作温度的电阻，可以提高电迁移行为和电性能。
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4.发明申请TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE 有权通过适应线路电阻的温度依赖性在半导体中形成金属线的技术公开(公告)号：US20080268265A1
公开(公告)日：2008-10-30
申请号：US11952522
申请日：2007-12-07
IPC分类号： B32B15/20
CPC分类号： H01L21/76877 , H01L21/76834 , H01L21/76864 , H01L21/76883 , Y10T428/31678
摘要： By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
摘要翻译： 通过适当地将缺陷引入诸如铜的高导电材料中，可以显着地修改电阻对温度行为，从而可以在先进的半导体器件的金属化结构中获得增强的电迁移行为和/或电性能。 电阻的缺陷相关部分可以适度增加，以便改变电阻对温度曲线的斜率，从而允许引入杂质原子以增强电迁移耐力，同时不会不适当地增加在工作温度下的整体电阻甚至甚至 降低在指定工作温度下的相应电阻。 因此，通过适当地设计目标工作温度的电阻，可以提高电迁移行为和电性能。
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公开(公告)号：US06953755B2
公开(公告)日：2005-10-11
申请号：US10677911
申请日：2003-10-02
IPC分类号： G01N23/04 , G01N23/223 , G01R31/28 , H01L21/44
CPC分类号： G01N23/04 , G01N23/223 , G01N2223/076
摘要： By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored. Moreover, displaying some of the measurement results as a quick motion representation enables the detection of subtle changes of characteristics of an interconnect structure in a highly efficient manner.
摘要翻译： 通过准备通过电子显微镜或X射线显微镜进行横截面分析的完全嵌入的互连结构样品，可以有效地监测降解机理。 此外，将一些测量结果显示为快速运动表示能够以高效的方式检测互连结构的特征的微妙变化。
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6.发明申请METHOD OF TESTING AN INTEGRITY OF A MATERIAL LAYER IN A SEMICONDUCTOR STRUCTURE 有权测试材料层在半导体结构中的完整性的方法公开(公告)号：US20080160654A1
公开(公告)日：2008-07-03
申请号：US11777355
申请日：2007-07-13
IPC分类号： H01L21/66
CPC分类号： H01L21/76868 , H01L22/12
摘要： A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.
摘要翻译： 一种方法包括提供半导体结构。 该半导体结构包括一特征，该特征包括形成在该特征上的第一材料和第二材料层。 半导体结构暴露于蚀刻剂。 蚀刻剂适于选择性地去除第一材料，使第二材料基本上保持不变。 在将半导体结构暴露于蚀刻剂之后，检测特征是否受蚀刻剂的影响。
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7.发明授权Method of testing an integrity of a material layer in a semiconductor structure 有权测试半导体结构中的材料层的完整性的方法公开(公告)号：US08058081B2
公开(公告)日：2011-11-15
申请号：US11777355
申请日：2007-07-13
IPC分类号： H01L21/66
CPC分类号： H01L21/76868 , H01L22/12
摘要： A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.
摘要翻译： 一种方法包括提供半导体结构。 该半导体结构包括一特征，该特征包括形成在该特征上的第一材料和第二材料层。 半导体结构暴露于蚀刻剂。 蚀刻剂适于选择性地去除第一材料，使第二材料基本上保持不变。 在将半导体结构暴露于蚀刻剂之后，检测特征是否受蚀刻剂的影响。
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