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9 条记录 (耗时 0.019 秒)

    Apparatus and method for implementing a communications port
    1.
    发明申请
    Apparatus and method for implementing a communications port 有权
    用于实现通信端口的装置和方法

    公开(公告)号：US20070112992A1

    公开(公告)日：2007-05-17

    申请号：US11280155

    申请日：2005-11-16

    申请人： Morten Schanke ,  Knut Tvete ,  Steinar Forsmo

    发明人： Morten Schanke ,  Knut Tvete ,  Steinar Forsmo

    IPC分类号： G06F13/40

    CPC分类号： G06F13/387

    摘要： There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

    摘要翻译： 描述了用于实现通信端口的装置和方法。 该装置包括：核心，其可以通过使用时分多路复用来划分多个子端口中的端口的数据传输容量来将端口划分成多个子端口。 每个子端口分配相应的数据传输能力。

    Apparatus and method for a core for implementing a communications port
    2.
    发明授权
    Apparatus and method for a core for implementing a communications port 有权
    用于实现通信端口的核心的装置和方法

    公开(公告)号：US07660926B2

    公开(公告)日：2010-02-09

    申请号：US11280155

    申请日：2005-11-16

    申请人： Morten Schanke ,  Knut Tvete ,  Steinar Forsmo

    发明人： Morten Schanke ,  Knut Tvete ,  Steinar Forsmo

    IPC分类号： G06F13/372

    CPC分类号： G06F13/387

    摘要： There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

    摘要翻译： 描述了用于实现通信端口的装置和方法。 该装置包括：核心，其可以通过使用时分多路复用来划分多个子端口中的端口的数据传输容量来将端口划分成多个子端口。 每个子端口分配相应的数据传输能力。

    Input and output buffering
    5.
    发明授权
    Input and output buffering 有权
    输入和输出缓冲

    公开(公告)号：US07436845B1

    公开(公告)日：2008-10-14

    申请号：US10863038

    申请日：2004-06-08

    申请人： Hans Rygh ,  Morten Schanke ,  Ola Torudbakken ,  Steinar Forsmo

    发明人： Hans Rygh ,  Morten Schanke ,  Ola Torudbakken ,  Steinar Forsmo

    IPC分类号： H04L12/56

    CPC分类号： H04L49/35 ,  H04L49/253 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/358 ,  H04L49/55

    摘要： An Infiniband device is provided. The device has a plurality of input/output ports. Each port has associated therewith an input buffer for storage of a packet received at that port. Each port also has associated therewith a plurality of output buffers for storage of a packet transmitted from an input buffer via a switching matrix. Each port is arranged to share its associated plurality of output ports with at least one other port. Each input buffer is also associated with a single output buffer of each shared plurality of output buffers. A packet received at an input buffer is transmitted to all associated output buffers via the switching matrix in parallel with an output buffer select signal. The output buffer select signal is sent to less than all of the associated output buffers, any output buffer not receiving the output buffer select signal is configured to discard the packet transmitted from the input buffer.

    摘要翻译： 提供Infiniband设备。 该设备具有多个输入/输出端口。 每个端口都具有与其相关联的用于存储在该端口处接收的分组的输入缓冲器。 每个端口还具有多个输出缓冲器，用于存储经由开关矩阵从输入缓冲器发送的分组。 每个端口被布置成与至少一个其他端口共享其相关联的多个输出端口。 每个输入缓冲器也与每个共享的多个输出缓冲器的单个输出缓冲器相关联。 在输入缓冲器处接收的分组经由与输出缓冲器选择信号并行的开关矩阵发送到所有相关联的输出缓冲器。 输出缓冲器选择信号被发送到小于所有关联的输出缓冲器，没有接收输出缓冲器选择信号的任何输出缓冲器被配置为丢弃从输入缓冲器发送的数据包。

    VCRC checking and generation
    6.
    发明授权
    VCRC checking and generation 有权
    VCRC检查和生成

    公开(公告)号：US07483442B1

    公开(公告)日：2009-01-27

    申请号：US10863013

    申请日：2004-06-08

    申请人： Ola Torudbaken ,  Hans Rygh ,  Steinar Forsmo ,  Morten Schanke

    发明人： Ola Torudbaken ,  Hans Rygh ,  Steinar Forsmo ,  Morten Schanke

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/50 ,  G06F13/00

    CPC分类号： H04L49/15 ,  H04L49/101 ,  H04L49/253 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/358

    摘要： An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.

    摘要翻译： 可以提供Infiniband开关。 交换机可以具有用于确定接收到的分组的输出虚拟通道的输入端口逻辑单元，并且用于将所确定的输出虚拟通道的描述符存储在未被分组的校验和字段保护的分组字段中。 交换机还可以具有路由单元，用于将接收的分组传送到对应于所确定的输出虚拟通道的输出端口。 此外，交换机可以具有输出端口逻辑单元，用于同时检查通过路由单元传送的分组的完整性，并且计算用于校验和的新值，并将描述符移动到正确的分组字段，该字段包括在计算 校验和。

    Data transfer
    7.
    发明授权
    Data transfer 有权
    数据传输

    公开(公告)号：US07242736B2

    公开(公告)日：2007-07-10

    申请号：US10438898

    申请日：2003-05-15

    申请人： Morten Schanke ,  Steinar Forsmo ,  Ali Bozkaya ,  Hans Rygh

    发明人： Morten Schanke ,  Steinar Forsmo ,  Ali Bozkaya ,  Hans Rygh

    IPC分类号： H04L25/00

    CPC分类号： H04L49/9031 ,  H04J3/0629 ,  H04J3/0632 ,  H04L25/14 ,  H04L49/90 ,  H04L49/901

    摘要： A receiver for digital data is provided. The receiver comprises a ring buffer operable to store received data. The receiver also comprises a write pointer controller for the buffer, operable to control the writing of received data into the buffer, and a read pointer controller for the buffer, operable to control the reading of data from the buffer. The receiver further comprises a pointer adjustment controller operable, in response to a detection of a special data indicator, to control at least one of the write pointer controller and the read pointer controller using forward looking operable to foresee a data location within the buffer corresponding to a future read location of the buffer.

    摘要翻译： 提供数字数据接收机。 接收机包括可操作用于存储接收数据的环形缓冲器。 接收机还包括用于缓冲器的写指针控制器，用于控制将接收的数据写入缓冲器，以及用于缓冲器的读指针控制器，用于控制从缓冲器读取数据。 接收机还包括指针调节控制器，其可响应于特殊数据指示符的检测而操作，以使用前瞻性来控制写入指针控制器和读取指针控制器中的至少一个，可操作以预见缓冲器内的数据位置对应于 缓冲区的未来读取位置。

    Service level to virtual lane mapping
    8.
    发明授权
    Service level to virtual lane mapping 有权
    服务级别到虚拟通道映射

    公开(公告)号：US07400590B1

    公开(公告)日：2008-07-15

    申请号：US10862985

    申请日：2004-06-08

    申请人： Hans Rygh ,  Steinar Forsmo ,  Ola Torudbakken

    发明人： Hans Rygh ,  Steinar Forsmo ,  Ola Torudbakken

    IPC分类号： H04L12/28 ,  H04L12/56

    CPC分类号： H04L12/462 ,  H04L45/00 ,  H04L45/302

    摘要： An Infiniband device can be provided. The device can have an input port for receiving a packet. The port can be operable to extract a destination descriptor and a quality of service requirement descriptor for the packet and simultaneously to determine an output port of the device for onward transmission of the packet on the basis of the destination descriptor and to determine an output port virtual lane for each output port of the device on the basis of the quality of service requirement descriptor. The port can additionally be operable subsequently to use the determined output port to select between the determined output port virtual lanes.

    摘要翻译： 可以提供Infiniband设备。 该设备可以具有用于接收分组的输入端口。 该端口可用于提取分组的目的地描述符和服务质量要求描述符，并同时确定用于根据目的地描述符向前发送分组的设备的输出端口，并且确定输出端口虚拟 根据服务质量要求描述符设备的每个输出端口的通道。 该端口还可以随后可操作地使用确定的输出端口在所确定的输出端口虚拟通道之间进行选择。

    Multiprocessor interconnection in scalable coherent interface
    9.
    发明授权
    Multiprocessor interconnection in scalable coherent interface 失效
    可扩展连贯接口中的多处理器互连

    公开(公告)号：US5819075A

    公开(公告)日：1998-10-06

    申请号：US502687

    申请日：1995-07-14

    申请人： Steinar Forsmo

    发明人： Steinar Forsmo

    IPC分类号： G06F13/42 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G06F13/4256

    摘要： A scalable coherent interface (SCI) architecture delivers a high speed unidirectional signal from one SCI node to a next successive SCI node. The signal includes a data portion, e.g., SCI symbol, and a clock portion, e.g., a symbol separator. The clock portion indicates when the data portion may be sampled when collecting a sequence of SCI symbols. Relative timing between bits of the data portion and between the data portion as a whole and the symbol separator clock becomes skewed during transmission. The receiving node introduces delay in the clock portion as a function of detected stability in a synchronizing packet. A plurality of data registers are cyclicly written in response to the delayed clock portion whereby a single one of said registers at a given time is concurrently clocked and enabled. A control device monitors enable signals applied to the registers and in coordinated fashion cyclically reads SCI symbols therefrom. As a result, signal transmission from a transmitting time domain to a receiving time domain includes a time domain mapping and de-skewing function.

    摘要翻译： 可扩展相干接口（SCI）架构提供从一个SCI节点到下一个连续SCI节点的高速单向信号。 信号包括数据部分，例如SCI符号，以及时钟部分，例如符号分离器。 时钟部分指示当收集SCI符号序列时数据部分何时被采样。 在传输期间，数据部分的位之间和数据部分之间以及符号分离器时钟的相对定时变得倾斜。 接收节点将时钟部分中的延迟作为同步分组中检测到的稳定性的函数引入。 响应于延迟的时钟部分循环地写入多个数据寄存器，由此在给定时间的单个寄存器同时被计时和使能。 控制装置监视施加到寄存器并以协调方式循环读取SCI符号的使能信号。 结果，从发送时域到接收时域的信号传输包括时域映射和去偏移功能。