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    Semiconductor memory device using high-density and high-speed MOS elements
    1.
    发明授权
    Semiconductor memory device using high-density and high-speed MOS elements 失效
    半导体存储器件采用高密度高速MOS元件

    公开(公告)号：US4990999A

    公开(公告)日：1991-02-05

    申请号：US416494

    申请日：1989-10-03

    申请人： Motohiro Oishi ,  Kunio Matsudaira ,  Keiji Fukumura ,  Shigemi Sasada

    发明人： Motohiro Oishi ,  Kunio Matsudaira ,  Keiji Fukumura ,  Shigemi Sasada

    IPC分类号： H01L21/3205 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/108 ,  H01L27/112

    CPC分类号： H01L27/10805

    摘要： A semiconductor memory device in which MOS transistors are used. The device has diffusion lines and polysilicon lines formed on a semiconductor substrate, first and second insulating films covering the diffusion lines and the polysilicon lines, respectively. The diffusion lines extend at intervals and parallel with each other, and constitute bit lines of the memory device. The polysilicon lines extend at intervals, intersect the diffusion lines, and constitute word lines of the memory device. Metal wiring lines are formed on the second insulating film are each positioned over every other diffusion line in such a manner as to extend along the corresponding diffusion line, each metal wiring line being electrically connected to the corresponding diffusion line through a contact hole. Two regions of two adjacent diffusion lines that are underneath the two intersections of these two adjacent diffusion lines and one polysilicon line constitute the source region and the drain region of one MOS transistor, and a portion of the polysilicon line which is between the source region and the drain region constitutes the gate of the MOS transistor. Thus, MOS transistors of the device can be disposed with an increased density, without involving any reduction in the operation speed of the device.

    摘要翻译： 使用MOS晶体管的半导体存储器件。 该器件具有形成在半导体衬底上的扩散线和多晶硅线，分别覆盖扩散线和多晶硅线的第一和第二绝缘膜。 扩散线以间隔延伸并且彼此平行，并且构成存储器件的位线。 多晶硅线以间隔延伸，与扩散线相交，并构成存储器件的字线。 形成在第二绝缘膜上的金属布线各自沿着相应的扩散线延伸设置在每隔一个扩散线上，每条金属布线通过接触孔与相应的扩散线电连接。 在两个相邻扩散线的两个交点之下的两个相邻扩散线的两个区域和一个多晶硅线构成一个MOS晶体管的源极区域和漏极区域，以及位于源极区域和 漏区构成MOS晶体管的栅极。 因此，器件的MOS晶体管可以以更高的密度布置，而不会降低器件的工作速度。

    Sense circuit of a semiconductor memory device
    2.
    发明授权
    Sense circuit of a semiconductor memory device 失效
    半导体存储器件的检测电路

    公开(公告)号：US4774692A

    公开(公告)日：1988-09-27

    申请号：US122452

    申请日：1987-11-19

    申请人： Motohiro Oishi ,  Kunio Matsudaira ,  Keiji Fukumura

    发明人： Motohiro Oishi ,  Kunio Matsudaira ,  Keiji Fukumura

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C7/00 ,  H03K3/01

    CPC分类号： G11C7/12 ,  G11C7/067

    摘要： A sense circuit of a semiconductor memory transistor includes a bit line connected to a memory cell which stores "1" or "0". The sense circuit includes a MOS transistor which has its gate connected to the bit line, its source connected to ground voltage and its drain connected to a supply voltage through a load MOS transistor. The sense circuit also includes a compensating circuit for compensating the voltage at the bit line when the ground voltage has fluctuated. For example, the compensating circuit includes a pull-up circuit for pulling up the voltage at the bit line when the ground voltage has shifted to the positive side and a pull-down circuit for pulling down the voltage at the bit line when the ground voltage has shifted to the negative side, thereby maintaining the relative voltage relationship between the voltage at the bit line and the ground voltage at a proper value.

    摘要翻译： 半导体存储晶体管的感测电路包括连接到存储“1”或“0”的存储单元的位线。 感测电路包括其栅极连接到位线的MOS晶体管，其源极接地电压，其漏极通过负载MOS晶体管连接到电源电压。 感测电路还包括补偿电路，用于在接地电压波动时补偿位线处的电压。 例如，补偿电路包括：上拉电路，用于在接地电压转移到正极时提升位线上的电压;以及下拉电路，用于在接地电压 已经转移到负侧，从而将位线处的电压和接地电压之间的相对电压关系保持在适当的值。

    MEMORY CONFIGURATION OF A COMPOSITE MEMORY DEVICE
    3.
    发明申请
    MEMORY CONFIGURATION OF A COMPOSITE MEMORY DEVICE 有权
    复合存储器件的存储器配置

    公开(公告)号：US20090091984A1

    公开(公告)日：2009-04-09

    申请号：US12333674

    申请日：2008-12-12

    申请人： Minoru FUKUDA ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    发明人： Minoru FUKUDA ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16

    摘要： The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of other flash memory array is enable when the plural sector flash memory array is gained access.

    摘要翻译： 本发明涉及一种复合闪速存储装置，它包括被分成多个扇区的多扇区快闪存储器阵列，该多个扇区闪速存储器阵列是闪速存储器件的最小擦除单元，存储控制命令的闪存阵列， 复合闪速存储器件和/或唯一的复合闪速存储器件，并且共享多扇区闪速存储器阵列的I / O线，当获得多个扇区闪速存储器阵列时，其他闪速存储器阵列的读取操作成立。

    Electrically alterable non-volatile semiconductor memory device
    4.
    发明授权
    Electrically alterable non-volatile semiconductor memory device 失效
    电可变非易失性半导体存储器件

    公开(公告)号：US6104057A

    公开(公告)日：2000-08-15

    申请号：US138891

    申请日：1998-08-24

    申请人： Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe ,  Yoichi Sakai

    发明人： Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe ,  Yoichi Sakai

    IPC分类号： G11C16/04 ,  H01L29/423 ,  H01L29/76

    CPC分类号： G11C16/0491 ,  G11C16/0425 ,  G11C16/0433 ,  H01L29/42324

    摘要： An electrically alterable non-volatile memory device is disclosed. In the device architecture of the memory device, control gates are formed, divided corresponding to the blocks and interconnected independently within each block, to further be connected to a metal gate line through block select MOS transistors which are formed on a semiconductor substrate between the blocks. All gate electrodes of the block select MOS transistors which are connected to the control gates interconnected as above within each block are further connected each other. These block select transistors can be controlled by applying erase block signals such as, EBS0, EBS1 and so on, to respective transistors. In addition, the control gates are further connected to a decoder such that some of these control gates may be selected through metal control gate lines. With the block select transistors together with the metal control gate line provided as above, erasing can be achieved in the unit of memory cells which are connected to a metal control gate line within a block.

    摘要翻译： 公开了一种电可更改的非易失性存储器件。 在存储器件的器件架构中，形成控制栅极，对应于块并且在每个块内独立互连，以进一步通过形成在块之间的半导体衬底上的块选择MOS晶体管连接到金属栅极线 。 在各块内连接到如上互连的控制栅极的块选择MOS晶体管的所有栅极电极彼此进一步连接。 可以通过将诸如EBS0，EBS1等的擦除块信号施加到相应的晶体管来控制这些块选择晶体管。 此外，控制栅极进一步连接到解码器，使得这些控制栅极中的一些可以通过金属控制栅极线选择。 通过块选择晶体管与如上所述设置的金属控制栅极线一起，可以以连接到块内的金属控制栅极线的存储单元为单位实现擦除。

    Memory configuration of a composite memory device
    7.
    发明授权
    Memory configuration of a composite memory device 有权
    复合存储设备的内存配置

    公开(公告)号：US07969791B2

    公开(公告)日：2011-06-28

    申请号：US12650762

    申请日：2009-12-31

    申请人： Minoru Fukuda ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    发明人： Minoru Fukuda ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16

    摘要： The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

    摘要翻译： 本发明涉及一种复合闪速存储装置，它包括被分成多个扇区的多扇区快闪存储器阵列，该多个扇区闪速存储器阵列是闪速存储器件的最小擦除单元，存储控制命令的闪存阵列， 复合闪速存储器件和/或唯一的复合闪速存储器件，并且共享多扇区快闪存储器阵列的I / O线，当获得多个扇区闪速存储器阵列时，闪存阵列的读取操作成立。

    Memory configuration of a composite memory device
    8.
    发明授权
    Memory configuration of a composite memory device 有权
    复合存储设备的内存配置

    公开(公告)号：US07672172B2

    公开(公告)日：2010-03-02

    申请号：US12333674

    申请日：2008-12-12

    申请人： Minoru Fukuda ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    发明人： Minoru Fukuda ,  Hiroaki Nakanishi ,  Kunio Matsudaira ,  Masahiro Matsuo ,  Hirohisa Abe

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16

    摘要： The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

    摘要翻译： 本发明涉及一种复合闪速存储装置，它包括被分成多个扇区的多扇区快闪存储器阵列，该多个扇区闪速存储器阵列是闪速存储器件的最小擦除单元，存储控制命令的闪存阵列， 复合闪速存储器件和/或唯一的复合闪速存储器件，并且共享多扇区快闪存储器阵列的I / O线，当获得多个扇区闪速存储器阵列时，闪存阵列的读取操作成立。