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    METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC)
    5.
    发明申请
    METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) 审中-公开
    使用错误校正码（ECC）编码的缓存标签的直接匹配的方法和设备

    公开(公告)号：US20110161783A1

    公开(公告)日：2011-06-30

    申请号：US12647932

    申请日：2009-12-28

    申请人： Dinesh Somasekhar ,  Jeffrey L. Miller ,  Gunjan H. Pandya ,  Tsung-Yung Chang ,  Wei Wu ,  Shih-Lien L. Lu

    发明人： Dinesh Somasekhar ,  Jeffrey L. Miller ,  Gunjan H. Pandya ,  Tsung-Yung Chang ,  Wei Wu ,  Shih-Lien L. Lu

    IPC分类号： G06F11/10 ,  G06F12/06

    CPC分类号： G06F11/1064 ,  G06F12/0895

    摘要： An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined.

    摘要翻译： 这里描述了直接匹配编码标签的装置和方法。 输入标签地址用纠错码（ECC）编码，以获得编码的传入标签。 编码的输入标签直接与存储的编码标签进行比较; 在一个示例中，该比较结果在编码的输入标签和存储的编码标签之间产生m位差。 在一个所描述的实施例中，ECC能够校正k位并检测k + 1位。 结果，如果m位差在2k + 2位之内，则检测有效的代码编码标签。 例如，如果m位差小于诸如k位的命中阈值，则确定命中，而如果m位差大于诸如k + 1位的未命中阈值， 那么一个小姐是决定的。

    DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)
    6.
    发明申请
    DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) 有权
    双端口静态随机存取存储器（SRAM）

    公开(公告)号：US20140269019A1

    公开(公告)日：2014-09-18

    申请号：US13842086

    申请日：2013-03-15

    申请人： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

    发明人： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412

    摘要： In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

    摘要翻译： 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

    Bitline floating during non-access mode for memory arrays
    7.
    发明授权
    Bitline floating during non-access mode for memory arrays 有权
    位线在内存阵列的非访问模式下浮动

    公开(公告)号：US08982659B2

    公开(公告)日：2015-03-17

    申请号：US12645623

    申请日：2009-12-23

    申请人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    发明人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C11/413

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C11/413

    摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    摘要翻译： 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

    BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS
    8.
    发明申请
    BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS 有权
    用于存储阵列的非访问模式下的位线浮动

    公开(公告)号：US20110149666A1

    公开(公告)日：2011-06-23

    申请号：US12645623

    申请日：2009-12-23

    申请人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

    发明人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C11/413

    摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    摘要翻译： 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。