摘要:
Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
摘要:
A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.
摘要:
A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.
摘要:
A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.
摘要:
A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.
摘要:
A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.
摘要:
A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.
摘要:
A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
摘要:
A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
摘要:
A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.