公开(公告)号：US20060236146A1

公开(公告)日：2006-10-19

申请号：US10559672

申请日：2004-06-03

申请人： Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

发明人： Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

IPC分类号： G06F1/12

CPC分类号： G06F1/10 ,  G01R31/31725 ,  G01R31/31726 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2005/0026

摘要： A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.

摘要翻译： 一种数字系统（1），其根据单个或多个时钟信号执行数字处理以传送指定的基本功能，并且包括分别插入到多个时钟电路中的多个延迟元件（4），用于提供时钟 信号，并且分别由用于根据控制信号指示的值改变延迟时间的电路元件构成，以及多个保持电路（5），用于保持多个控制信号被提供给多个延迟元件 。 多个保持电路具有由这些保持电路保持的多个控制信号值，根据概率搜索方法由外部设备（6-8）改变，数字系统（1）从可变输出 - 电压电源（14），使数字系统的基本功能满足规定的规格。

公开(公告)号：US4789835A

公开(公告)日：1988-12-06

申请号：US70130

申请日：1987-07-02

申请人： Richard F. Herlein

发明人： Richard F. Herlein

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  H03K17/00 ,  G06K5/04

CPC分类号： G11C7/22 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31928 ,  G01R31/31935 ,  G01R31/31937 ,  H03K5/131 ,  H03K5/14 ,  G01R31/31926 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

摘要翻译： 一种能够在自动测试系统中以精确期望的时间提供信号的系统。 该装置包括存储与基本时间延迟有关的信息的基本延迟存储器，而游标存储器存储与基本时间延迟相关的定时校正的信息。 基本延迟存储器控制计数器，而校正存储器控制游标去偏移装置，用于进一步延迟来自计数器的输出信号。 为了防止游标存储器的进位影响基本延迟存储器，游标存储器的最高有效位与基本延迟存储器的最低有效位具有相同的意义。 游标存储器的最高有效位也被连接以驱动计数器，实际上为计数器提供两个最低有效位，并且使单个基本延迟存储器能够控制多于一个信号定时路径。

公开(公告)号：US4651038A

公开(公告)日：1987-03-17

申请号：US611266

申请日：1984-05-17

申请人： Ronald L. Cline ,  John G. Campbell

发明人： Ronald L. Cline ,  John G. Campbell

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  H03K5/159 ,  G06G7/10

CPC分类号： H03K5/14 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31928 ,  G01R31/31935 ,  G01R31/31937 ,  H03K5/131 ,  G01R31/31926 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent. The reference voltage source for the load current source is a modified band-gap regulator comprising a regulating transistor, a current source pair of transistors Q1 and Q2, and first, second, and third resistors. The third resistor changes the current relationships to provide the desired output voltage and temperature coefficient.

摘要翻译： 尽管温度有很大的变化，但是在门的输出节点稳定信号定时的电路技术。 在具有开关部分和射极跟随器的栅极中，开关部分内的栅极延迟的温度依赖性可以通过适当地控制提供射极跟随器输出节点的负载电流源的温度特性来抵消。 负载电流源包括电流源电阻器，具有耦合到输出节点的集电极的电流源晶体管和参考电压源。 电压源而不是具有如已知温度补偿配置中的零温度系数，被配置为具有选择的温度系数，以通过射极跟随器在延迟中提供温度依赖性，其抵消通过开关的延迟的温度依赖性 使得总门延迟基本上与温度无关。 用于负载电流源的参考电压源是修改的带隙调节器，其包括调节晶体管，晶体管Q1和Q2的电流源对以及第一，第二和第三电阻器。 第三个电阻改变电流关系以提供所需的输出电压和温度系数。

公开(公告)号：US5073733A

公开(公告)日：1991-12-17

申请号：US510702

申请日：1990-04-18

申请人： Masaya Tanno ,  Masato Onaya

发明人： Masaya Tanno ,  Masato Onaya

IPC分类号： H03H17/08 ,  H03H17/00 ,  H03K5/00 ,  H03K5/135

CPC分类号： H03K5/135 ,  H03K2005/00247 ,  H03K2005/0026 ,  H03K2005/00267 ,  H03K2005/00273

摘要： A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

公开(公告)号：US4675546A

公开(公告)日：1987-06-23

申请号：US893033

申请日：1986-08-04

申请人： John R. Shaw

发明人： John R. Shaw

IPC分类号： H03K5/04 ,  H03K5/13 ,  H03K3/017

CPC分类号： H03K5/04 ,  H03K5/131 ,  H03K2005/00058 ,  H03K2005/00247 ,  H03K2005/0026

摘要： An inexpensive edge programmable timing signal generator for generating timing signals having complete edge programmability for accommodating incrementally adjustable variable pulse widths. The timing circuit is particularly useful in memory testing devices, where generation of a multiplicity of clock phases is required. A delay register delays an input timing signal generated by a coarse timing circuit by a predetermined amount of time, and a pair of rising and falling edge delay lines receive and delay the input and delayed timing signals by further predetermined amounts of time. The signals output from the rising and falling edge delay lines are applied to an OR gate, the output of which is applied to an EXCLUSIVE OR gate for selectively inverting the signal output from the OR gate. The circuit is inexpensive and takes up very little circuit board area.

摘要翻译： 一种便宜的边缘可编程定时信号发生器，用于产生具有完整边缘可编程性的定时信号，以适应增量可调的可变脉冲宽度。 定时电路在需要生成多个时钟相位的存储器测试装置中特别有用。 延迟寄存器将由粗定时电路产生的输入定时信号延迟预定的时间量，并且一对上升沿和下降沿延迟线接收并延迟输入和延迟的定时信号进一步预定的时间量。 从上升沿和下降沿延迟线输出的信号被施加到或门，其输出被施加到异或门以选择性地反相从或门输出的信号。 电路价格便宜，电路板面积很小。

公开(公告)号：US4635256A

公开(公告)日：1987-01-06

申请号：US611446

申请日：1984-05-17

申请人： Richard F. Herlein

发明人： Richard F. Herlein

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  G01R31/28

CPC分类号： H03K5/131 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31928 ,  G01R31/31935 ,  G01R31/31937 ,  H03K5/14 ,  G01R31/31926 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries. Multiple test vectors for a given test period are permitted and error correlator decodes error signals produced by incorrect output signals from the device under test. The error correlator decodes these error signals and logs them in a memory location corresponding to the proper test vector.

摘要翻译： 用于高速集成电路测试系统的格式化电路控制定时数据脉冲到被测设备的输入端的应用，产生选通信号以控制连接到正被测试设备的输出端的比较器，并提供解码电路 从正在测试的设备接收的错误信号。 格式化电路通过单独的信号线将所有关键信号路径路由到被测设备，从而允许补偿每个信号路径的不同传播延迟。 正在测试的设备的输入转换和输出选通信号在系统时钟上并不是及时固定的，而是参考它。 这使得驱动数据周期和比较数据周期不太依赖于系统时钟，并允许它们重叠并交叉测试周期边界。 允许给定测试周期的多个测试向量，并且误差相关器解码来自被测器件的错误输出信号产生的误差信号。 误差相关器对这些误差信号进行解码并将其记录在与正确的测试向量相对应的存储器位置。

公开(公告)号：US4849702A

公开(公告)日：1989-07-18

申请号：US282830

申请日：1988-12-08

申请人： Burnell G. West ,  Richard F. Herlein

发明人： Burnell G. West ,  Richard F. Herlein

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14

CPC分类号： G11C7/22 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31928 ,  G01R31/31935 ,  G01R31/31937 ,  H03K5/131 ,  H03K5/14 ,  G01R31/31926 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issues a signal that designates the end of the period.

摘要翻译： 定时子系统10包括若干测试周期发生器，用于向被测设备提供各种定时信号。 主，次要和自由运行周期发生器各自向多路复用器18提供各种定时信号，多路复用器18将定时信号选择性地连接到定时发生器20.中央处理单元28向周期发生器和定时发生器提供数据以定义它们各自的定时 信号。 由主时期发生器12产生的定时信号定义了总体测试速率。 次周期发生器14在主时钟信号的周期内产生多个定时信号以允许更高的时钟速率。 与主时钟周期无关的定时信号由自由运行周期发生器16产生。外部同步器电路26提供从被测器件22到主周期发生器的反馈回路。 参考驱动器触发延迟电路27提供用于校准定时发生器的装置。 三个周期发生器中的每一个包括交替地产生重叠定时信号的两个互连的定时间隔发生器30和40。 每个定时间隔发生器包括停止重启振荡器32，计数器34和延迟线游标36​​。在接收到起始信号时，振荡器停止并重新启动以将其时钟脉冲对准起始信号。 振荡器输出时钟计数器，当达到预选号码时，该计数器向游标器提供信号。 游标游标延迟计数器信号，并发出一个指定周期结束的信号。

公开(公告)号：US4837521A

公开(公告)日：1989-06-06

申请号：US135782

申请日：1987-12-21

申请人： Richard F. Herlein ,  Jeffrey A. Davis

发明人： Richard F. Herlein ,  Jeffrey A. Davis

IPC分类号： G01R31/3183 ,  G01R31/319 ,  H03K5/00 ,  H03K5/13

CPC分类号： H03K5/131 ,  G01R31/3191 ,  G01R31/31922 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

摘要翻译： 公开了一种能够在自动测试系统中以精确期望的时间提供信号的系统。 该装置包括基本延迟存储器，其存储表示时间延迟的较高位的信息，而游标存储器存储与时间延迟的低位比特相关的信息。 偏移存储器可存储校准数据。 基本延迟存储器控制独立信号路径中的至少两个计数器，而游标和偏移存储器控制适当的去偏移单元，以根据需要进一步延迟计数器输出信号。 该系统能够共享资源，但不需要重复加载校正数据进行偏移校正操作。

公开(公告)号：US4271483A

公开(公告)日：1981-06-02

申请号：US929797

申请日：1978-07-31

申请人： John L. E. Baldwin ,  Terence E. Corbyn

发明人： John L. E. Baldwin ,  Terence E. Corbyn

IPC分类号： H03H11/26 ,  G06F5/06 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135

CPC分类号： G06F5/06 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/00241 ,  H03K2005/00247 ,  H03K2005/0026

摘要： Digital delay apparatus for variable delay uses a shift register fixed delay driving a random access memory variable delay. A variable modulus counter controls the read-write addressing, whereby the difference between addresses sets the variable delay of the random access memory. The random access memory capacity is small relative to the shift register for increased efficiency.

摘要翻译： 用于可变延迟的数字延迟装置使用移位寄存器固定延迟来驱动随机存取存储器可变延迟。 可变模数计数器控制读写寻址，由此地址之间的差设置随机存取存储器的可变延迟。 随机存取存储器容量相对于移位寄存器较小，以提高效率。

公开(公告)号：US4675562A

公开(公告)日：1987-06-23

申请号：US611451

申请日：1984-05-17

申请人： Richard F. Herlein ,  Jeffrey A. Davis ,  E. James Cotriss

发明人： Richard F. Herlein ,  Jeffrey A. Davis ,  E. James Cotriss

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  H03K3/86 ,  H03K17/26

CPC分类号： G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31928 ,  G01R31/31935 ,  G01R31/31937 ,  H03K5/131 ,  H03K5/14 ,  G01R31/31926 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

摘要翻译： 用于延迟电信号的装置包括一系列级，每一级用于延迟信号。 更粗糙的级将信号延迟预定基本延迟间隔的倍数，并且更细的级提供对延迟的微调。 精细级包括整数N个延迟元件，总共提供大于基本延迟间隔的延迟间隔，由此精细延迟间隔补偿制造公差，以通过后制造测量来精确校准组合系统。 在一个实施例中，每个延迟级包括提供延迟间隔的抽头传输线，在另一个使用的斜坡发生器中。