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    SERIAL BUS TRANSMISSION SYSTEM
    1.
    发明申请
    SERIAL BUS TRANSMISSION SYSTEM 有权
    串行总线传输系统

    公开(公告)号：US20110142066A1

    公开(公告)日：2011-06-16

    申请号：US12988939

    申请日：2009-04-20

    申请人： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    发明人： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    IPC分类号： H04B7/212

    CPC分类号： H04L12/4035

    摘要： A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

    摘要翻译： 主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。 当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行 在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

    Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
    2.
    发明授权
    Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program 失效
    信号定时调整装置，信号定时调整系统，信号定时调整量设定程序以及存储该程序的存储介质

    公开(公告)号：US07447289B2

    公开(公告)日：2008-11-04

    申请号：US10809374

    申请日：2004-03-26

    申请人： Munehiro Uratani ,  Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi ,  Masahiro Murakawa

    发明人： Munehiro Uratani ,  Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi ,  Masahiro Murakawa

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H03L7/087

    摘要： Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

    摘要翻译： 根据来自电路块的数据通过测量寄存器获取的定时和来自数据块的数据的定时，测量数据到电路块的数据输入与来自数据块的数据的输出之间的延迟时间 电路块由数据锁存器获取。 LSI测试仪设置好的电压调整值，使得每个电路块的延迟时间被平均。 根据由调整电压产生电路产生的电压，选择器选择与电压调节值相一致的电压。 所选择的电压被施加到每个时钟定时调整电路的CMOS晶体管的阱。 因此调整输入时钟的定时之间的延迟时间。

    Serial bus transmission system
    3.
    发明授权
    Serial bus transmission system 有权
    串行总线传输系统

    公开(公告)号：US08493991B2

    公开(公告)日：2013-07-23

    申请号：US12988939

    申请日：2009-04-20

    申请人： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    发明人： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    IPC分类号： H04B7/212 ,  H04B1/44 ,  H04Q11/00 ,  H04J3/00 ,  H04L12/40 ,  H04L7/00 ,  H04W4/00

    CPC分类号： H04L12/4035

    摘要： A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

    摘要翻译： 主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。 当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行 在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

    Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method
    6.
    发明申请
    Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method 审中-公开
    数字系统，数字系统的时钟信号调整方法，以调整方式执行的记录介质记录处理程序

    公开(公告)号：US20060236146A1

    公开(公告)日：2006-10-19

    申请号：US10559672

    申请日：2004-06-03

    申请人： Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

    发明人： Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

    IPC分类号： G06F1/12

    CPC分类号： G06F1/10 ,  G01R31/31725 ,  G01R31/31726 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2005/0026

    摘要： A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.

    摘要翻译： 一种数字系统（1），其根据单个或多个时钟信号执行数字处理以传送指定的基本功能，并且包括分别插入到多个时钟电路中的多个延迟元件（4），用于提供时钟 信号，并且分别由用于根据控制信号指示的值改变延迟时间的电路元件构成，以及多个保持电路（5），用于保持多个控制信号被提供给多个延迟元件 。 多个保持电路具有由这些保持电路保持的多个控制信号值，根据概率搜索方法由外部设备（6-8）改变，数字系统（1）从可变输出 - 电压电源（14），使数字系统的基本功能满足规定的规格。

    Packet data comparator as well as virus filter, virus checker and network system using the same
    8.
    发明授权
    Packet data comparator as well as virus filter, virus checker and network system using the same 失效
    分组数据比较器以及病毒过滤器，病毒检测器和网络系统使用相同

    公开(公告)号：US08429749B2

    公开(公告)日：2013-04-23

    申请号：US12055651

    申请日：2008-03-26

    申请人： Eiichi Takahashi ,  Masahiro Yasuda ,  Yosuke Iijima ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

    发明人： Eiichi Takahashi ,  Masahiro Yasuda ,  Yosuke Iijima ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

    IPC分类号： H04L29/06

    CPC分类号： H04L63/145 ,  G06F21/562 ,  G06F21/57

    摘要： A network system by the present invention can quickly detect viruses and does not easily become a new cause of vulnerability. A packet data comparator branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched data with the stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched data with the stored data and performs the matching with a logical operation configured with known collation patterns, a notification packet matching unit which compares the branched data with the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units. Moreover, a virus filter, a virus checker, and a secure network system are realized by using the present invention.

    摘要翻译： 本发明的网络系统可以快速检测病毒，不容易成为新的漏洞。 分组数据比较器将输入的分组数据分成三个分支，并且包括附加模式匹配单元，其将分支数据与存储的数据进行比较，并且与存储在可重写存储区域中的对照模式进行匹配，固定模式匹配单元， 数据与存储的数据进行匹配，并且执行与已知对照模式配置的逻辑操作的匹配;通知分组匹配单元，其将分支数据与所存储的数据进行比较并找到通知分组;以及身份检测聚合单元， 各匹配单位。 此外，通过使用本发明来实现病毒过滤器，病毒检查器和安全网络系统。

    Virus check device and system
    9.
    发明申请
    Virus check device and system 审中-公开
    病毒检查设备和系统

    公开(公告)号：US20060242686A1

    公开(公告)日：2006-10-26

    申请号：US10546157

    申请日：2004-02-20

    申请人： Kenji Toda ,  Tetsuya Higuchi ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Masaya Iwata

    发明人： Kenji Toda ,  Tetsuya Higuchi ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Masaya Iwata

    IPC分类号： H04L9/32 ,  G06F17/30 ,  G06F15/16

    CPC分类号： G06F21/567 ,  G06F21/564 ,  H04L63/1416 ,  H04L63/145

    摘要： The present invention detects a computer virus at high speed from digital data acquired through a network using hardware in virus monitoring. With the invention, in an information processing terminal 002 capable of communicating with other information processing apparatus through a communication network 005, a virus checking apparatus 001 constructed of a hardware circuit is disposed in the side of an input channel of the network 005 and a virus is checked from input data from the network 005 by the virus checking apparatus 001. In order to change a virus pattern collated with the input data by hardware, the hardware circuit is detachably mounted or a rewritable logic device is used in the hardware circuit. The virus pattern of the logic device can be rewritten by sending virus definition information of a server 004 or control data generated based on this information to the virus checking apparatus 001.

    摘要翻译： 本发明通过使用病毒监视中的硬件通过网络获取的数字数据高速检测计算机病毒。 通过本发明，在能够通过通信网络005与其他信息处理装置进行通信的信息处理终端002中，由硬件电路构成的病毒检查装置001设置在网络005的输入信道侧，病毒 由病毒检查装置001从网络005的输入数据检查。 为了通过硬件改变与输入数据进行比较的病毒模式，硬件电路可拆卸地安装，或在硬件电路中使用可重写逻辑器件。 通过将服务器004的病毒定义信息或基于该信息产生的控制数据发送到病毒检查装置001，可以重写逻辑设备的病毒码。

    Timing adjustment of clock signals in a digital circuit
    10.
    发明授权
    Timing adjustment of clock signals in a digital circuit 失效
    数字电路中时钟信号的时序调整

    公开(公告)号：US06658581B1

    公开(公告)日：2003-12-02

    申请号：US09519463

    申请日：2000-03-06

    申请人： Eiichi Takahashi ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

    发明人： Eiichi Takahashi ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

    IPC分类号： H04L700

    CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K2005/00039 ,  H03K2005/00058 ,  H04L7/0037

    摘要： A digital system that performs a specified function by performing digital processing according to one or more clock signals is provided with a plurality of delay elements which are respectively inserted in a plurality of clock circuits that supply the clock signals in the digital system and each of which is composed of a circuit element that changes a delay time according to a value indicated by a control signal, and a plurality of holding circuits that hold a plurality of control signals to be given to the plurality of delay elements. In the plurality of holding circuits, a value of the control signals held by these holding circuits is changed by external devices according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.

    摘要翻译： 通过执行根据一个或多个时钟信号的数字处理来执行指定功能的数字系统被提供有多个延迟元件，它们分别插入在数字系统中提供时钟信号的多个时钟电路中， 由根据由控制信号指示的值改变延迟时间的电路元件和保持要提供给多个延迟元件的多个控制信号的多个保持电路组成。 在多个保持电路中，这些保持电路保持的控制信号的值根据概率搜索技术被外部设备改变，使得数字系统相对于操作定时正确地操作。