公开(公告)号：US12198864B2

公开(公告)日：2025-01-14

申请号：US18218303

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita Kitahara ,  Yuta Saito ,  Noriyuki Ookawa ,  Riyousuke Akazawa ,  Takefumi Takahashi ,  Masahiro Wakashima ,  Yuta Kurosu ,  Akito Mori

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/08 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US11984265B2

公开(公告)日：2024-05-14

申请号：US17947446

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takumi Endou ,  Sho Watanabe ,  Akito Mori ,  Masahiro Wakashima

IPC: H01G4/12 ,  H01G4/008

CPC classification number: H01G4/1218 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes dielectric layers made of a ceramic material and internal electrode layers laminated therein. The internal electrode layers each include dielectric columns provided therein. A solid solution layer in which S is solidly dissolved is provided at an interface between each of the dielectric columns and each of the internal electrode layers.

公开(公告)号：US11721490B2

公开(公告)日：2023-08-08

申请号：US17495853

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu Tsutsui ,  Yuta Kurosu ,  Daiki Fukunaga ,  Yuta Saito ,  Masahiro Wakashima

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G13/00 ,  C04B35/468 ,  H01G4/008

CPC classification number: H01G4/30 ,  C04B35/468 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1227 ,  H01G13/00 ,  C04B2235/66

Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.

公开(公告)号：US11367573B2

公开(公告)日：2022-06-21

申请号：US17131893

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu Tsutsui ,  Yuta Kurosu ,  Daiki Fukunaga ,  Yuta Saito ,  Masahiro Wakashima

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.

公开(公告)号：US12119183B2

公开(公告)日：2024-10-15

申请号：US18524673

申请日：2023-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita Kitahara ,  Yuta Saito ,  Noriyuki Ookawa ,  Riyousuke Akazawa ,  Takefumi Takahashi ,  Masahiro Wakashima ,  Yuta Kurosu ,  Akito Mori

IPC: H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, base electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers and each including glass and copper, and plated layers respectively provided on an outer side of the base electrode layers. A protective layer including sulfur is provided between the glass included in the base electrode layers and the plated layers.

公开(公告)号：US12009157B2

公开(公告)日：2024-06-11

申请号：US18218300

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita Kitahara ,  Yuta Saito ,  Noriyuki Ookawa ,  Riyousuke Akazawa ,  Takefumi Takahashi ,  Masahiro Wakashima ,  Yuta Kurosu ,  Akito Mori

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1218

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US11837414B2

公开(公告)日：2023-12-05

申请号：US17495854

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro Wakashima ,  Yuta Saito ,  Akito Mori

IPC: H01G4/38 ,  H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

CPC classification number: H01G4/38 ,  H01G4/1227 ,  H01G4/2325 ,  H01G4/248 ,  H01G4/30

Abstract: A multilayer ceramic capacitor package accommodating multilayer ceramic capacitors includes a carrier tape that is elongated and includes recess pockets at equal or substantially equal intervals in a longitudinal direction, a cover tape that is elongated and attached to the carrier tape to cover an opening of each of the pockets, and the multilayer ceramic capacitors respectively accommodated in the pockets. In the multilayer ceramic capacitor package, in adjacent multilayer ceramic capacitors, a difference in densities of surfaces on an opening side of the pockets is about 0% or more and about 4% or less.

公开(公告)号：US11257619B2

公开(公告)日：2022-02-22

申请号：US16549088

申请日：2019-08-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro Wakashima

IPC: H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a laminated body including dielectric layers and internal electrode layers alternately laminated in a width direction, and first and second external electrodes on a bottom surface of the laminated body. Among ridges located on a side of an upper surface of the laminated body of an inner layer generating capacitance, a ridge located on the side of a first end surface is a first ridge, and a ridge located on the side of a second end surface is a second ridge. When r1 is a curvature radius of the first ridge at a central position in the width direction of the laminated body, and r2 is a curvature radius of the second ridge at the central position in the width direction of the laminated body, conditions of r1≤50 μm and r2≤50 μm are satisfied.

公开(公告)号：US12154724B2

公开(公告)日：2024-11-26

申请号：US17947271

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akito Mori ,  Masahiro Wakashima ,  Sho Watanabe ,  Takumi Endou

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including internal electrode layers and inner dielectric layers laminated alternately, and internal electrode layers at both ends thereof in a lamination direction, and outer dielectric layers covering the inner layer portion, and two external electrodes on both end surfaces of the multilayer body in a length direction intersecting the lamination direction. The inner and outer dielectric layers each include grains, and a difference between an average grain size of grains in the inner dielectric layers and an average grain size of grains in the outer dielectric layers is about 100 nm or less.

公开(公告)号：US11869724B2

公开(公告)日：2024-01-09

申请号：US18103054

申请日：2023-01-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta Kurosu ,  Yuta Saito ,  Masahiro Wakashima ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/248 ,  H01G4/12 ,  H01G4/008

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/2325 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.