公开(公告)号：US11721490B2

公开(公告)日：2023-08-08

申请号：US17495853

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu Tsutsui ,  Yuta Kurosu ,  Daiki Fukunaga ,  Yuta Saito ,  Masahiro Wakashima

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G13/00 ,  C04B35/468 ,  H01G4/008

CPC classification number: H01G4/30 ,  C04B35/468 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1227 ,  H01G13/00 ,  C04B2235/66

Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.

公开(公告)号：US11367573B2

公开(公告)日：2022-06-21

申请号：US17131893

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu Tsutsui ,  Yuta Kurosu ,  Daiki Fukunaga ,  Yuta Saito ,  Masahiro Wakashima

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.

公开(公告)号：US11239030B2

公开(公告)日：2022-02-01

申请号：US16566994

申请日：2019-09-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideyuki Hashimoto ,  Daiki Fukunaga ,  Takayuki Yao ,  Takehisa Sasabayashi

IPC: H01G4/12 ,  H01G4/30 ,  H01G4/10 ,  H01G4/005

Abstract: An electronic component includes a laminate including internal electrodes alternately laminated in a lamination direction with dielectric layers interposed therebetween. The laminate includes main surfaces opposite to each other in the lamination direction, side surfaces opposite to each other in a width direction, and end surfaces opposite to each other in a length direction, and external electrodes provided on surfaces of the laminate and electrically connected to the internal electrodes. Each of the dielectric layers includes Ti and Mg. When a cross section including the length direction and the width direction of the laminate is viewed from the lamination direction, side margin portions in which the internal electrodes do not exist each include a dielectric including Ti and Mg with a molar ratio in each of the side margin portions smaller than a molar ratio of Mg to Ti included in each of the dielectric layers.

公开(公告)号：US10923279B2

公开(公告)日：2021-02-16

申请号：US16656899

申请日：2019-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/005

Abstract: A multilayer ceramic electronic component includes a laminate, a first external electrode on a first end surface of the laminate, and a second external electrode on a second end surface of the laminate. The laminate includes a central layer portion in which each first internal electrode layer and each second internal electrode layer oppose each other with a dielectric ceramic layer therebetween, peripheral layer portions sandwiching the central layer portion in a lamination direction, and side margins sandwiching the central layer portion and the peripheral layer portions in a width direction. The side margins each include an inner layer disposed closest to the laminate, an outer layer disposed farthest from the laminate, and a buffer layer disposed between the inner layer and the outer layer.

公开(公告)号：US10720281B2

公开(公告)日：2020-07-21

申请号：US16568573

申请日：2019-09-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideaki Tanaka ,  Daiki Fukunaga ,  Koji Moriyama

IPC: H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.

公开(公告)号：US12237114B2

公开(公告)日：2025-02-25

申请号：US18519243

申请日：2023-11-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta Kurosu ,  Yuta Saito ,  Masahiro Wakashima ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US12020867B2

公开(公告)日：2024-06-25

申请号：US18110396

申请日：2023-02-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Hideaki Tanaka ,  Masahiro Wakashima ,  Daisuke Hamada ,  Hironori Tsutsumi ,  Satoshi Maeno ,  Ryota Aso ,  Koji Moriyama ,  Akihiro Tsuru

IPC: H01G4/12 ,  H01G4/008 ,  H01G4/012 ,  H01G4/224 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G4/1227 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/224 ,  H01G4/2325 ,  H01G4/30

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

公开(公告)号：US11450484B2

公开(公告)日：2022-09-20

申请号：US17131899

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro Wakashima ,  Yuta Saito ,  Yuta Kurosu ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

Abstract: In a multilayer ceramic capacitor includes, in a plane including a center portion in a length direction, and a stacking direction and a width direction of a first dielectric ceramic layer, where a thickness at a center portion in the stacking direction is T1, a thickness at an end of the first dielectric ceramic layer in the width direction is T2, and respective thicknesses between an end of a first internal electrode layer in the length direction not connected to a second external electrode, and the second external electrode, and between an end of the second internal electrode layer in the length direction not connected to the first external electrode, and the first external electrode is T3, a difference in thickness between T1 and T2 is within about 10% of T1, and a thickness of T3 is greater than T1 and T2 and a difference thereof is about 10% or more of T1 and T2.

公开(公告)号：US11322307B2

公开(公告)日：2022-05-03

申请号：US17131898

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Yuta Kurosu ,  Yuta Saito ,  Masahiro Wakashima ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/248 ,  H01G4/12 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer.

公开(公告)号：US10714263B2

公开(公告)日：2020-07-14

申请号：US16285283

申请日：2019-02-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideaki Tanaka ,  Daiki Fukunaga ,  Koji Moriyama

IPC: H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.