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公开(公告)号：US6021128A
公开(公告)日：2000-02-01
申请号：US814649
申请日：1997-03-10
申请人： Mutsumi Hosoya , Morihito Miyagi , Willy Hioe , Akihiko Takase , Takahiko Kozaki , Toshikazu Nishino
发明人： Mutsumi Hosoya , Morihito Miyagi , Willy Hioe , Akihiko Takase , Takahiko Kozaki , Toshikazu Nishino
IPC分类号： H04Q3/00 , H04L12/70 , H04L12/931 , H04L12/933 , H04Q3/52 , H04Q11/04 , H04L12/50 , H04L12/56 , H04Q11/00
CPC分类号： H04Q11/0478 , H04L2012/5649
摘要： An asynchronous transfer mode switching system for improving switching throughput and averting complicated and difficult timing design. In operation, synchronous cell strings from external transmission lines are converted to asynchronous cell strings which are switched by a space-division switch array. The switched asynchronous cell strings are reconverted to synchronous cell strings for output onto external transmission lines. The space-division switch array comprises a plurality of unit switches in stages, each unit switch having input terminals and output terminals. The unit switches each include a timing control circuit that causes a switching operation to start upon detecting two states concurrently: a stored state of a cell to be switched, and a storage-ready state of a destination for the switched cell. The scheme allows the system to operate in an asynchronous manner.
摘要翻译： 一种异步传输模式切换系统，用于提高交换吞吐量并避免复杂而困难的时序设计。 在操作中，来自外部传输线的同步单元串被转换成由空分开关阵列切换的异步单元串。 交换的异步单元串被重新转换为同步单元串，以输出到外部传输线。 空分开关阵列分为多个单元开关，每个单元开关具有输入端子和输出端子。 单元开关每个包括定时控制电路，其在同时检测两个状态时使开关操作开始：待切换的单元的存储状态和用于切换的单元的目的地的存储就绪状态。 该方案允许系统以异步方式运行。
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公开(公告)号：US5570368A
公开(公告)日：1996-10-29
申请号：US409691
申请日：1995-03-24
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.
摘要翻译： 单元多路复用器包括用于对多个输入线提供的ATM信元进行时分多路复用的复用单元，用于将连续相应于输入线的多路复用单元输出的单元信号存储在缓冲存储器中的读控制器， 以与ATM单元结构同步的数据块的形式从缓冲存储器读取存储在缓冲存储器中的单元信号;以及单元描绘控制器，用于检测从缓冲存储器读出的数据块的描画状态，通知读取控制器 选择对应于与预定单元结构同步地读出的数据块的检测结果对应的描画控制信息到所述输出行，其中，所述读取控制器确定与所述读取控制信息相对应地读出的数据块的读取开始地址 输入线根据描绘控制信息通知 由细胞描绘控制器编辑。
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公开(公告)号：US5768274A
公开(公告)日：1998-06-16
申请号：US678659
申请日：1996-07-11
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.
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公开(公告)号：US5923657A
公开(公告)日：1999-07-13
申请号：US31776
申请日：1998-02-27
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
CPC分类号： H04L12/5601 , H04L49/255 , H04L49/3081 , H04L2012/5647 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
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公开(公告)号：US06256311B1
公开(公告)日：2001-07-03
申请号：US09031775
申请日：1998-02-27
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04J314
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
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公开(公告)号：US06252877B1
公开(公告)日：2001-06-26
申请号：US09094678
申请日：1998-06-15
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译： 一种ATM交换系统，包括对应于输出队列的PVC分配电路。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与存储的标识信息相同的PVC识别信息的随后到达的小区被输入到输出缓冲器，并且剩余突发数据的单元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。
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公开(公告)号：US07095726B2
公开(公告)日：2006-08-22
申请号：US09960999
申请日：2001-09-25
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system includes PVC allocation circuits 13-i corresponding to output queues 14-i is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has a room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are “input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译： ATM交换系统包括对应于输出队列14 -i的PVC分配电路13 -i。 在每个突发数据的前导单元的到达时，如果输出线具有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与存储的识别信息相同的PVC识别信息的随后到达的小区被“输入到输出缓冲器”，并且剩余突发数据的单元都被丢弃，即使当多个突发数据竞争相同的输出线时， 除了首先到达的入站突发数据之外的所有小区被丢弃的事实防止了小区在预定带宽内的输入，并且由于输出队列溢出而使受到小区丢弃影响的突发数据进行本地化。
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公开(公告)号：US5886982A
公开(公告)日：1999-03-23
申请号：US604615
申请日：1996-02-21
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/851 , H04L12/911 , H04L12/927 , H04L12/931 , H04L12/937 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译： 公开了一种包括对应于输出队列的PVC分配电路的ATM交换系统。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与存储的标识信息相同的PVC识别信息的随后到达的小区被输入到输出缓冲器，并且剩余突发数据的单元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。
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公开(公告)号：US06389026B1
公开(公告)日：2002-05-14
申请号：US09031775
申请日：1998-02-27
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04J314
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells, having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译： 一种ATM交换系统，包括对应于输出队列的PVC分配电路。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与所存储的标识信息相同的PVC识别信息的随后到达的信元被输入到输出缓冲器，并且剩余突发数据的信元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。
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公开(公告)号：US06021130A
公开(公告)日：2000-02-01
申请号：US94675
申请日：1998-06-15
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/851 , H04L12/911 , H04L12/927 , H04L12/931 , H04L12/937 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译： 一种ATM交换系统，包括对应于输出队列的PVC分配电路。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与存储的标识信息相同的PVC识别信息的随后到达的小区被输入到输出缓冲器，并且剩余突发数据的单元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。
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