公开(公告)号：US20230402351A1

公开(公告)日：2023-12-14

申请号：US18329845

申请日：2023-06-06

申请人： NEXPERIA B.V.

发明人： Ricardo Yandoc ,  Matthew Anthony ,  Zhou Zhou ,  Adam Brown

IPC分类号： H01L23/495 ,  H01L21/48

CPC分类号： H01L23/49562 ,  H01L23/49503 ,  H01L21/4825

摘要： According to the disclosure a semiconductor package assembly is proposed, at least including: a lead metallic frame; a semiconductor die structure being mounted on a die pad of the lead metallic frame; at least a first bond clip connected with the semiconductor die structure; at least a further bond clip connected with the die pad of the lead metallic frame via a solder junction; and the die pad is provided with at least one recess near the connection with the at least further bond clip for accommodating solder for the solder junction. The disclosure also pertains to a method for manufacturing such a semiconductor package assembly.

公开(公告)号：US20230178507A1

公开(公告)日：2023-06-08

申请号：US18061130

申请日：2022-12-02

申请人： NEXPERIA B.V.

发明人： Randolph Estal Flauta ,  Kan Wae Lam ,  Wai Hung William Hor ,  Zhou Zhou

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/19 ,  H01L24/96 ,  H01L24/03 ,  H01L24/05 ,  H01L24/20 ,  H01L21/561 ,  H01L21/568 ,  H01L2924/13091 ,  H01L2224/96 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/03462 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/214 ,  H01L2924/1421

摘要： This disclosure relates to a new package concept that eliminates the need for epoxy or epoxy solder used in traditional clip/lead frame-based power packages. The disclosure overcomes this disadvantage in clip-based packages by depositing the interconnect structure directly to the bod pads. The formation of the interconnect done at lower temperature leads to lower stress induced onto the die. Another advantage of the present disclosure is that semiconductor dies packaged using a method according to the present disclosure will have smaller footprint as the pads are directly built up/deposited. Another advantage of the method according to the present disclosure is that it allows large scale, i.e., panel level processing. Such a panel may include multiple ICs, or transistor or any other semiconductor devices.

公开(公告)号：US20240096769A1

公开(公告)日：2024-03-21

申请号：US18467779

申请日：2023-09-15

申请人： NEXPERIA B.V.

发明人： Haibo Fan ,  Zhou Zhou ,  Chi Ho Leung

IPC分类号： H01L23/495 ,  H01L21/48

CPC分类号： H01L23/49582 ,  H01L21/4821 ,  H01L21/561

摘要： The disclosure provides a method for manufacturing a semiconductor package assembly, which results in a semiconductor package assembly with a more even distributed stress concentrations, reduced solder crack occurrences and limited solder filler joint connections.

公开(公告)号：US20230223320A1

公开(公告)日：2023-07-13

申请号：US18153688

申请日：2023-01-12

申请人： NEXPERIA B.V.

发明人： Ricardo Yandoc ,  Adam Brown ,  Zhou Zhou

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/34 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/49503 ,  H01L23/562 ,  H01L23/34 ,  H01L23/3121 ,  H01L21/4842 ,  H01L23/49568

摘要： A semiconductor device package and a method for manufacturing the same is provided. The semiconductor device package includes a semiconductor die having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component, a stress relief substrate fixedly and electrically connected to the die terminal, and a clip lead. The substrate is configured to provide an electrical short between the clip lead and the die terminal. The stress relief substrate may form an interface between the clip lead and the semiconductor die and can thereby reduce stress exerted on the semiconductor die by the clip lead.

公开(公告)号：US20230146666A1

公开(公告)日：2023-05-11

申请号：US17982619

申请日：2022-11-08

申请人： NEXPERIA B.V.

发明人： Zhou Zhou ,  Haibo Fan ,  Chi Ho Leung

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L23/49555 ,  H01L21/56 ,  H01L24/32

摘要： An electronic package and method for manufacturing is provided. The package includes an electronic component having a terminal, a solidified molding compound encapsulating the electronic component, a lead including an inner and a mounting portion. The molding compound includes a first recess at or near a perimeter of a bottom surface of the mounting portion, exposing a portion of a bottom surface of the inner portion arranged near the mounting portion, and/or a second recess at the perimeter of the bottom surface of the mounting portion, the second recess exposing a portion of a side surface of the mounting portion extending between the top and the bottom surface of the mounting portion. The package provides more exposed lead space for a larger solder covering area using the first and/or second recess. Thus, solder strain accumulation is reduced or mitigated, and reliability of the electronic package can be enhanced.