Battery management architectures for flow batteries

    公开(公告)号:US11522383B2

    公开(公告)日:2022-12-06

    申请号:US16436710

    申请日:2019-06-10

    Abstract: Systems and methods for managing flow batteries utilize a battery management controller (BMC) coupled between a flow battery and a DC/DC converter, which is coupled to an electrical grid or a photovoltaic device via an inverter. The inverter converts an AC voltage to a first DC voltage and the DC/DC converter steps down the first DC voltage to a second DC voltage. The BMC includes a first power route, a second power route, and a current source converter coupled to the second power route. The BMC initializes the flow battery with a third DC voltage using the current source converter until a sensing circuit senses that the voltage of the flow battery has reached a predetermined voltage. The sensing circuit may include a capacitor, which has a small capacitance and is coupled across each cell of the flow battery, coupled in series between two resistors having very large resistances.

    POWER CONVERTERS AND METHODS OF CONTROLLING SAME

    公开(公告)号:US20220181975A1

    公开(公告)日:2022-06-09

    申请号:US17437037

    申请日:2020-02-25

    Abstract: A power converter converts a medium-voltage output from a solar module to an appropriate voltage to power a solar tracker system. The power converter includes a voltage divider having at least two legs, a first semiconductor switch subassembly coupled in parallel with a first leg of the voltage divider, and a second semiconductor switch subassembly coupled in parallel with a second leg of the voltage divider. The power converter may be a unidirectional or a bidirectional power converter. In implementations, the signals for driving the semiconductor switches of the first and second semiconductor switch subassemblies may be shifted out of phase from each other. In implementations, if the bus voltages to the semiconductor switches are not balanced, the pulse width of the driving signal of the semiconductor switch supplied with the higher bus voltage is decreased for at least one cycle.

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