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公开(公告)号：US11595052B2
公开(公告)日：2023-02-28
申请号：US17623613
申请日：2019-07-26
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Dongbing Fu , Zhengbo Huang , Yabo Ni , Jian'an Wang , Guangbing Chen
摘要： A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
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公开(公告)号：US11595004B2
公开(公告)日：2023-02-28
申请号：US17057698
申请日：2019-05-13
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Dongbing Fu
摘要： A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.
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3.发明授权公开(公告)号：US11115039B2
公开(公告)日：2021-09-07
申请号：US17057702
申请日：2019-05-13
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Dongbing Fu
摘要： The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.
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公开(公告)号：US10951220B2
公开(公告)日：2021-03-16
申请号：US16620879
申请日：2018-07-18
发明人： Yong Zhang , Ting Li , Zhengbo Huang , Yabo Ni , Dongbing Fu
摘要： The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.
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公开(公告)号：US11936378B2
公开(公告)日：2024-03-19
申请号：US17925323
申请日：2021-01-06
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Yabo Ni , Dongbing Fu , Jian'an Wang , Guangbing Chen
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.
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公开(公告)号：US11664794B2
公开(公告)日：2023-05-30
申请号：US17609415
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Guangbing Chen , Dongbing Fu , Zicheng Xu
CPC分类号： H03K5/2472 , H03K3/037
摘要： The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.
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7.发明授权公开(公告)号：US11349489B2
公开(公告)日：2022-05-31
申请号：US17602994
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： Yong Zhang , Ting Li , Zhengbo Huang , Yabo Ni , Dongbing Fu
摘要： An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.
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8.发明授权公开(公告)号：US10979066B1
公开(公告)日：2021-04-13
申请号：US16497806
申请日：2017-09-11
发明人： Zhengbo Huang , Ting Li , Yong Zhang , Ruzhang Li , Guangbing Chen , Yabo Ni
摘要： The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.
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