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公开(公告)号：US11936378B2
公开(公告)日：2024-03-19
申请号：US17925323
申请日：2021-01-06
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Yabo Ni , Dongbing Fu , Jian'an Wang , Guangbing Chen
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.
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公开(公告)号：US10291245B2
公开(公告)日：2019-05-14
申请号：US15742835
申请日：2015-08-20
发明人： Jie Pu , Gangyi Hu , Xiaofeng Shen , Xueliang Xu , Dongbing Fu , Ruitao Zhang , Youhua Wang , Yuxin Wang , Guangbing Chen , Ruzhang Li
摘要： The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.
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3.发明申请公开(公告)号：US20180041221A1
公开(公告)日：2018-02-08
申请号：US15555071
申请日：2015-04-09
发明人： Daiguo Xu , Shiliu Xu , Gangyi Hu , Guangbing Chen , Lu Liu
CPC分类号： H03M1/442 , H03M1/068 , H03M1/069 , H03M1/1245 , H03M1/468
摘要： An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.
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公开(公告)号：US11239852B2
公开(公告)日：2022-02-01
申请号：US17257011
申请日：2018-07-25
发明人： Jie Pu , Gangyi Hu , Jian'an Wang , Guangbing Chen , Liang Li , Ting Li , Daiguo Xu , Xingfa Huang , Xi Chen , Tiehu Li , Youhua Wang
摘要： The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
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公开(公告)号：US10483358B2
公开(公告)日：2019-11-19
申请号：US16068098
申请日：2016-04-01
发明人： Kaizhou Tan , Gangyi Hu , Zhaohuan Tang , Jianan Wang , Yonghui Yang , Yi Zhong , Yang Cao , Yong Liu , Kunfeng Zhu
IPC分类号： H01L29/40 , H01L29/78 , H01L29/861 , H01L21/02 , H01L29/06 , H01L29/10 , H01L29/36 , H01L29/872 , H01L29/66 , H01L21/311 , H01L21/321 , H01L21/3213
摘要： A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
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公开(公告)号：US10084470B2
公开(公告)日：2018-09-25
申请号：US15555071
申请日：2015-04-09
发明人： Daiguo Xu , Shiliu Xu , Gangyi Hu , Guangbing Chen , Lu Liu
CPC分类号： H03M1/442 , H03M1/068 , H03M1/069 , H03M1/1245 , H03M1/468
摘要： An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.
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公开(公告)号：US12044583B2
公开(公告)日：2024-07-23
申请号：US16636021
申请日：2017-09-11
发明人： Rongbin Hu , Jian'an Wang , Dongbing Fu , Guangbing Chen , Zhengping Zhang , Hequan Jiang , Gangyi Hu
CPC分类号： G01K7/01 , G01K15/005 , G01K2219/00
摘要： A digital temperature sensor circuit is disclosed. The digital temperature sensor circuit includes a proportional to the absolute temperature (PTAT) current source, generating a PTAT current proportional to absolute temperature; a sigma-delta modulation module, including an integrator, an analog-to-digital conversion unit, and a feedback digital-to-analog conversion unit; the integrator converts the PTAT current into temperature voltage; the analog-to-digital conversion unit compares the temperature voltage with a band gap reference voltage to generate a digital modulation signal with a duty ratio proportional to the temperature; the feedback digital-to-analog conversion unit adjusts the voltage input by the analog-to-digital conversion unit and controls the charging and discharging speed of the integrator; a digital filter, quantizing the digital modulation signal into a digital signal, and outputting the digital signal.
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公开(公告)号：US11323129B2
公开(公告)日：2022-05-03
申请号：US17257315
申请日：2018-12-13
发明人： Jie Pu , Gangyi Hu , Dongbing Fu , Zhengping Zhang , Liang Li , Ting Li , Daiguo Xu , Mingyuan Xu , Xiaofeng Shen , Xianjie Wan , Youhua Wang
摘要： The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
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公开(公告)号：US11320846B2
公开(公告)日：2022-05-03
申请号：US17258159
申请日：2018-12-13
发明人： Yan Wang , Gangyi Hu , Tao Liu , Jian'an Wang , Daiguo Xu , Guangbing Chen , Dongbing Fu
摘要： The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.
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公开(公告)号：US11595052B2
公开(公告)日：2023-02-28
申请号：US17623613
申请日：2019-07-26
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Dongbing Fu , Zhengbo Huang , Yabo Ni , Jian'an Wang , Guangbing Chen
摘要： A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
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