公开(公告)号：US09583589B1

公开(公告)日：2017-02-28

申请号：US14883238

申请日：2015-10-14

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Xiaobing Mei ,  Ling-Shine Lee ,  Michael D. Lange ,  Wayne Yoshida ,  Po-Hsin Liu

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L29/423 ,  H01L29/205 ,  H01L21/283

CPC classification number: H01L29/66462 ,  H01L21/0277 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7785

Abstract: A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.

Abstract translation: 一种用于制造用于FET器件的双凹槽栅极结构的方法，其包括提供具有多个半导体层并且在所述晶片上沉积EBL抗蚀剂层的半导体晶片。 该方法还包括图案化EBL抗蚀剂层以在EBL抗蚀剂层中形成开口，并执行第一湿蚀刻以在晶片中形成第一凹部。 所述方法还包括在所述EBL抗蚀剂层上沉积介电层并进入所述第一凹槽中并执行干蚀刻以去除所述第一凹槽中的所述介电层的一部分。 该方法还包括通过电介质层中的开口进行第二湿蚀刻以形成第二凹槽，并在第一和第二凹槽中以及EBL抗蚀剂层的开口中沉积栅极金属层以形成栅极端子。

公开(公告)号：US10727050B1

公开(公告)日：2020-07-28

申请号：US15488084

申请日：2017-04-14

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Vincent Gambin ,  Loan T. Le ,  Michael D. Lange ,  Jesse B. Tice

IPC: H01L21/02 ,  H01L21/324

Abstract: A method for wafer-level deposition of a semiconductor layer structure including at least one two-dimensional black phosphorus layer. The method includes providing a wafer substrate and a metal catalyst layer on the substrate. The method includes heating a phosphorus material to generate a P4 flux and heating the P4 flux to generate a P2 flux, where the P2 flux is deposited on the metal catalyst layer using molecular beam epitaxy or chemical vapor deposition. The process of depositing the black phosphorus layer can include adding a dopant or alloy to the P2 flux to modify the band gap of the phosphorus layer. The method includes heating the substrate to a temperature above a temperature that causes red phosphorus to evaporate from the substrate, but does not cause black phosphorus to evaporate from the substrate.