公开(公告)号：US20240209491A1

公开(公告)日：2024-06-27

申请号：US18597354

申请日：2024-03-06

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Rajashree Bhattacharya ,  Vincent Gambin

IPC: C23C14/08 ,  C23C14/34 ,  C23C14/50 ,  C23C14/58 ,  H01J37/34

CPC classification number: C23C14/08 ,  C23C14/3464 ,  C23C14/505 ,  C23C14/5806 ,  H01J37/3426

Abstract: A power limiter for limiting power provided to an electronic device. The power limiter includes a waveguide that receives an input signal to be sent to the electronic device, an LaCoO3 film formed to one side of the waveguide, an LaCoO3 film formed to an opposite side of the waveguide, a grounded element formed to one of the LaCoO3 films and a grounded element formed to the other LaCoO3 film. When the heat level in the LaCoO3 films is below a predetermined threshold, the LaCoO3 films are an insulator and the input signal propagates through the waveguide to the electronic device, and when the heat level in the LaCoO3 films goes above the threshold, the LaCoO3 films become conductive, and the input signal is shunted through the LaCoO3 films to the grounded elements.

公开(公告)号：US09735545B1

公开(公告)日：2017-08-15

申请号：US15206041

申请日：2016-07-08

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Yaochung Chen ,  Vincent Gambin ,  Xianglin Zeng

IPC: H01S5/00 ,  H01S5/183 ,  H01S5/187 ,  H01S5/042 ,  H01S5/343

CPC classification number: H01S5/18369 ,  H01S5/183 ,  H01S5/18308 ,  H01S5/18341 ,  H01S5/18344 ,  H01S5/18377 ,  H01S5/34313

Abstract: A vertical cavity surface emitting laser (VCSEL) including a substrate and a bottom distributed Bragg reflector (DBR) having a plurality of layers deposited on the substrate. The VCSEL also includes a first charge confining layer deposited on the bottom DBR, an active region deposited on the first charge confining layer, and a second charge confining layer deposited on the active region. A current blocking layer is provided on the second charge confining layer, and a top epitaxial DBR including a plurality of top epitaxial DBR layers is deposited on the current blocking layer. A top electrode is deposited on the top epitaxial DBR, a bottom electrode is deposited on the bottom DBR and adjacent to the active region, and a top dielectric DBR is deposited on the top epitaxial DBR and the top electrode.

公开(公告)号：US20220364219A1

公开(公告)日：2022-11-17

申请号：US17318519

申请日：2021-05-12

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Rajashree Bhattacharya ,  Vincent Gambin

IPC: C23C14/08 ,  C23C14/58

Abstract: A method for producing a LaCoO3 film on a substrate that includes positioning the substrate in a vacuum chamber, positioning a cobalt target in the vacuum chamber, positioning a lanthanum target in the vacuum chamber, providing oxygen in the vacuum chamber, and sputtering cobalt atoms off of the cobalt target and lanthanum atoms off of the lanthanum target so that the cobalt and lanthanum atoms interact with the oxygen to form the LaCoO3 film on the substrate. A power limiter that employs one or more LaCoO3 films is also disclosed.

公开(公告)号：US11488889B1

公开(公告)日：2022-11-01

申请号：US15671432

申请日：2017-08-08

Applicant: Northrop Grumman Systems Corporation

Inventor： John A. Starkovich ,  Jesse B. Tice ,  Vincent Gambin

IPC: H01L23/373

Abstract: Cubic BAs is used in semiconductors to improve the thermal characteristics of a device. The BAs is used in device layers to improve thermal conductivity. The BAs also provides thermal expansion characteristics that are compatible with other semiconductors and thereby further improves reliability. The substrates of the semiconductors may also include vias that contain BAs. The BAs in the vias may contact the BAs in the device layers. Some vias may have a surface area to volume ratio of greater than 10 to better assist with device heat dissipation.

公开(公告)号：US09484284B1

公开(公告)日：2016-11-01

申请号：US15072242

申请日：2016-03-16

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION ,  GENERAL ELECTRIC COMPANY

Inventor： Vincent Gambin ,  Benjamin D. Poust ,  Dino Ferizovic ,  Stanton E. Weaver ,  Gary D. Mandrusiak

IPC: H01L33/32 ,  H01L29/20 ,  H01L21/02 ,  H01L23/473 ,  H01L29/205 ,  H01L29/778 ,  H01L23/367 ,  H01L23/373 ,  H01L27/095 ,  H01L23/66 ,  H03F3/213 ,  H03F3/193 ,  H03F3/195

CPC classification number: H01L23/4735 ,  H01L23/367 ,  H01L23/3732 ,  H01L23/66 ,  H01L27/095 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/778 ,  H01L2223/6644 ,  H01L2223/6683

Abstract: A MMIC power amplifier circuit assembly comprised of a SiC substrate having a plurality of microchannels formed therein, where a diamond layer is provided within each of the microchannels. A plurality of GaN HEMT devices are provided on the substrate where each HEMT device is positioned directly opposite to a microchannel. A silicon manifold is coupled to the substrate and includes a plurality of micro-machined channels formed therein that include a jet impingement channel positioned directly adjacent each microchannel, a return channel directly positioned adjacent to each microchannel, a supply channel supplying a cooling fluid to the impingement channels and a return channel collecting heated cooling fluid from the supply channels so that an impingement jet is directed on to the diamond layer for removing heat generated by the HEMT devices.

Abstract translation: 一种由在其中形成有多个微通道的SiC衬底组成的MMIC功率放大器电路组件，其中金属层设置在每个微通道内。 在基板上设置多个GaN HEMT器件，其中每个HEMT器件直接与微通道相对。 硅歧管联接到衬底并且包括形成在其中的多个微加工通道，其包括直接邻近每个微通道定位的喷射冲击通道，与每个微通道相邻直接定位的返回通道，向冷却流体供应冷却流体的供应通道 冲击通道和从供应通道收集加热的冷却流体的返回通道，使得冲击射流被引导到金刚石层以去除由HEMT装置产生的热量。

公开(公告)号：US11784107B1

公开(公告)日：2023-10-10

申请号：US17952433

申请日：2022-09-26

Applicant: Northrop Grumman Systems Corporation

Inventor： John A. Starkovich ,  Jesse B. Tice ,  Vincent Gambin

IPC: H01L23/373

CPC classification number: H01L23/3735 ,  H01L23/3736

Abstract: A semiconductor device is provided with a first layer having a first layer conductive contact and being doped at a first concentration of a first dopant type. The first dopant type being a P type dopant. A second layer is on top the first layer and being doped at a second concentration of the first dopant type. The second concentration being less than the first concentration. A third layer is on top of the second layer and having a third layer conductive contact and being doped with a second dopant type, the second dopant type being an N type dopant. A fourth layer is on top of the third layer and having a fourth layer conductive contact and being doped with the first dopant type, wherein at least one of the first and second layers is a boron arsenide (BAs) layer.

公开(公告)号：US11018296B1

公开(公告)日：2021-05-25

申请号：US17012400

申请日：2020-09-04

Applicant: Northrop Grumman Systems Corporation

Inventor： Vincent Gambin ,  Rachel A. Koltun ,  Benjamin Heying

IPC: H01L45/00

Abstract: An exemplary semiconductor incorporates phase change material MoxW1-xTe2 that may be the semiconducting channel or may be part of a control terminal/gate of the semiconductor. The phase change material selectably being in one of metal and insulator phases depending on whether a voltage field greater than a predetermined phase change field is present at the phase change material. The properties of the semiconductor are varied depending on the phase of the phase change material.

公开(公告)号：US10811601B2

公开(公告)日：2020-10-20

申请号：US16254218

申请日：2019-01-22

Applicant: Northrop Grumman Systems Corporation

Inventor： Vincent Gambin ,  Rachel A. Koltun ,  Benjamin Heying

IPC: H01L45/00

Abstract: An exemplary semiconductor incorporates phase change material MoxW1-xTe2 that may be the semiconducting channel or may be part of a control terminal/gate of the semiconductor. The phase change material selectably being in one of metal and insulator phases depending on whether a voltage field greater than a predetermined phase change field is present at the phase change material. The properties of the semiconductor are varied depending on the phase of the phase change material.

公开(公告)号：US10727050B1

公开(公告)日：2020-07-28

申请号：US15488084

申请日：2017-04-14

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Vincent Gambin ,  Loan T. Le ,  Michael D. Lange ,  Jesse B. Tice

IPC: H01L21/02 ,  H01L21/324

Abstract: A method for wafer-level deposition of a semiconductor layer structure including at least one two-dimensional black phosphorus layer. The method includes providing a wafer substrate and a metal catalyst layer on the substrate. The method includes heating a phosphorus material to generate a P4 flux and heating the P4 flux to generate a P2 flux, where the P2 flux is deposited on the metal catalyst layer using molecular beam epitaxy or chemical vapor deposition. The process of depositing the black phosphorus layer can include adding a dopant or alloy to the P2 flux to modify the band gap of the phosphorus layer. The method includes heating the substrate to a temperature above a temperature that causes red phosphorus to evaporate from the substrate, but does not cause black phosphorus to evaporate from the substrate.

公开(公告)号：US09196703B2

公开(公告)日：2015-11-24

申请号：US14464406

申请日：2014-08-20

Applicant: Northrop Grumman Systems Corporation ,  The United States of America, as Represented by the Secretary of the Navy ,  The Regents of the University of California

Inventor： Karl D. Hobart ,  Tatyana I. Feygelson ,  Eugene I. Imhoff ,  Travis J. Anderson ,  Joshua D. Caldwell ,  Andrew D. Koehler ,  Bradford B. Pate ,  Marko J. Tadjer ,  Rajinder S. Sandhu ,  Vincent Gambin ,  Gregory Lewis ,  Ioulia Smorchkova ,  Mark Goorsky ,  Jeff McKay

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/76802 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3732 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/778 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.

Abstract translation: 一种用于制造诸如GaN高电子迁移率晶体管（HEMT）器件的半导体器件的方法，包括将热通孔蚀刻到半导体衬底的背面中并且沉积金刚石成核种子层跨越衬底的背面 。 该方法还包括用掩模层涂覆金刚石成核，并在衬底背面的平面部分上去除热通孔外部的掩模材料。 该方法包括去除平面部分上的金刚石成核层的部分，然后去除热通孔中掩模材料的剩余部分。 该方法然后包括在金刚石成核层的剩余部分上的热通孔内沉积体金刚石层，使得金刚石仅在基底的热通孔而不是平面部分上生长。