公开(公告)号：US20150084975A1

公开(公告)日：2015-03-26

申请号：US14038599

申请日：2013-09-26

Applicant: NVIDIA CORPORATION

Inventor： Steven J. HEINRICH ,  Eric T. ANDERSON ,  Jeffrey A. BOLZ ,  Jonathan DUNAISKY ,  Ramesh JANDHYALA ,  Joel MCCORMACK ,  Alexander L. MINKIN ,  Bryon S. NORDQUIST ,  Poornachandra RAO

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F2212/302 ,  G06T1/20 ,  G06T15/04 ,  G09G5/363

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract translation: 公开了用于在具有被配置为处理纹理存储器访问操作的第一部分的纹理处理流水线中执行存储器访问操作的方法和被配置为处理非纹理存储器访问操作的第二部分。 纹理单元接收存储器访问请求。 纹理单元确定存储器访问请求是否包括纹理存储器访问操作。 如果存储器访问请求包括纹理存储器访问操作，则纹理单元至少通过纹理处理流水线的第一部分来处理存储器访问请求，否则，纹理单元至少经由第二部分处理存储器访问请求 纹理处理流水线。 所公开方法的一个优点是可以将相同的处理和高速缓冲存储器用于纹理操作和对各种其他地址空间的加载/存储操作，导致减小的表面积和功率消耗。

公开(公告)号：US20150097851A1

公开(公告)日：2015-04-09

申请号：US14049557

申请日：2013-10-09

Applicant: NVIDIA CORPORATION

Inventor： Eric T. ANDERSON ,  Poornachandra RAO

IPC: G06T1/60 ,  G06T11/00

CPC classification number: G06T1/60

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Abstract translation: 纹理处理流水线被配置为将解码的纹理数据存储在高速缓存单元内，以加速纹理请求的处理。 当处理纹理请求时，纹理处理流水线查询缓存单元以确定所请求的数据是否驻留在高速缓存中。 如果数据不驻留在高速缓存单元中，则会发生高速缓存未命中。 纹理处理流水线然后从全局存储器中读取编码的纹理数据，对该数据进行解码，并根据缓存图将特定位置处的解码存储器的不同部分写入高速缓存单元。 如果数据实际上驻留在高速缓存单元中，则发生高速缓存命中，并且纹理处理流水线然后从高速缓存单元读取所请求的纹理数据的解码部分，并根据缓存映射结合这些部分。

公开(公告)号：US20150089284A1

公开(公告)日：2015-03-26

申请号：US14033383

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Philip Payman SHIRVANI ,  Peter SOMMERS ,  Eric T. ANDERSON

IPC: G06F11/20 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F1/30

Abstract: Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.

Abstract translation: 计算机和图形处理元件，通常串联连接，形成管道。 被称为di / dt节流阀的电路元件被插入在管线内的策略位置处，其中存在用于数据流从空闲状态转换到最大数据处理速率的潜力。 di / dt节流阀缓缓地将数据流从空闲率提升到典型值。 因此避免了不成比例的电流消耗和随之而来的电压下降，从而允许实现更高的操作频率。

公开(公告)号：US20140173258A1

公开(公告)日：2014-06-19

申请号：US13720746

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian FAHS ,  Eric T. ANDERSON ,  Nick BARROW-WILLIAMS ,  Shirish GADRE ,  Joel James MCCORMACK ,  Bryon S. NORDQUIST ,  Nirmal Raj SAXENA ,  Lacky V. SHAH

IPC: G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/3851 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0844 ,  G06F2209/5018 ,  G06F2212/604

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract translation: 可以将纹理处理流水线配置为服务于表示纹理数据访问操作或通用数据访问操作的存储器访问请求。 当纹理处理流水线接收到表示纹理数据访问操作的存储器访问请求时，纹理处理流水线可以基于纹理坐标来检索纹理数据。 当存储器访问请求表示通用数据访问操作时，纹理流水线从存储器访问请求中提取虚拟地址，然后基于虚拟地址检索数据。 纹理处理流水线还被配置为缓存代表一组线程检索的通用数据，然后在线程组退出时使该通用数据无效。

公开(公告)号：US20140173193A1

公开(公告)日：2014-06-19

申请号：US13720755

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Eric T. ANDERSON ,  Nick Barrow-Williams ,  Shirish GADRE ,  Joel James MCCORMACK ,  Bryon S. NORDQUIST ,  Nirmal Raj Saxena ,  Lacky V. Shah

IPC: G06F17/30 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1018

Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

Abstract translation: 配置为管理高速缓存单元的标签单元包括实现集合散列函数的聚结器。 集合散列函数将虚拟地址映射到特定的内容可寻址存储器单元（CAM）。 聚合器通过将虚拟地址分割成上部，中部和下部来实现集合散列函数。 上部分进一步分为偶数位和奇数索引位。 使用XOR树将偶数索引位减少到单个位，并且奇数索引以类似的方式减少。 这些单个位与虚拟地址的中间部分组合以提供识别特定CAM的CAM号码。 查询所识别的CAM以确定虚拟地址的标签部分的存在，指示高速缓存命中或高速缓存未命中。