公开(公告)号：US20170371822A9

公开(公告)日：2017-12-28

申请号：US14101246

申请日：2013-12-09

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

IPC: G06F13/40 ,  G06F12/123 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0864

CPC classification number: G06F13/404 ,  G06F12/0806 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1041

Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

公开(公告)号：US20140281297A1

公开(公告)日：2014-09-18

申请号：US14134148

申请日：2013-12-19

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  Chenghuan JIA ,  Cameron BUSCHARDT ,  Lucien DUNNING ,  Brian FAHS

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0664 ,  G06F12/0804 ,  G06F12/1009 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/657

Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

Abstract translation: 提供了技术，通过该技术可以在多PPU系统中的PPU存储器之间迁移存储器页面。 根据这些技术，UVM驱动程序确定特定存储器页面应该改变所有权状态和/或在一个PPU存储器和另一个PPU存储器之间迁移。 响应于该确定，UVM驱动程序启动对等体转换序列以使存储器页的所有权状态和/或位置改变。 各种对等体转换序列涉及修改一个或多个PPU的映射，以及将存储器页面从一个PPU存储器复制到另一个PPU存储器。 可以并行执行对等转换序列中的几个步骤，以提高处理速度。

公开(公告)号：US20150089207A1

公开(公告)日：2015-03-26

申请号：US14033385

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Robert OHANNESSIAN ,  Brian FAHS

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/30021 ,  G06F9/30036

Abstract: A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion. The parallel counter may then return the individual segment counts to the application, or combine those segment counts and return a register count to the application. Advantageously, applications that rely on population count operations may be accelerated. Further, increasing the number of segments in a given register may reduce the time needed to count the values in that register, thereby providing a scalable solution to population counting. Additionally, the architecture of the parallel counter is sufficiently flexible to allow both register counting and segment counting, thereby combining two separate functionalities into just one hardware unit.

Abstract translation: 并行计数器访问应用程序生成并存储在寄存器中的数据。 寄存器包括不同的段，包括应用数据的不同部分。 并行计数器被配置为以并行方式对具有特定特性的每个段内的值的数目进行计数。 然后，并行计数器可以将各个段计数返回到应用程序，或者将这些段计数结合起来，并向应用程序返回寄存器计数。 有利地，可以加速依赖于群体计数操作的应用。 此外，增加给定寄存器中的段的数量可以减少对该寄存器中的值进行计数所需的时间，从而为群体计数提供可扩展的解决方案。 另外，并行计数器的架构足够灵活，允许寄存器计数和段计数，从而将两个单独的功能组合成一个硬件单元。

公开(公告)号：US20140281364A1

公开(公告)日：2014-09-18

申请号：US14011643

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/301

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

公开(公告)号：US20140123146A1

公开(公告)日：2014-05-01

申请号：US13660799

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, JR. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

IPC: G06F9/46

CPC classification number: G06F9/5033 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/505 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US20170371802A9

公开(公告)日：2017-12-28

申请号：US14011643

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/301

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

公开(公告)号：US20170235491A1

公开(公告)日：2017-08-17

申请号：US15583920

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK ,  John MASHEY ,  Mark HAIRGROVE ,  Chenghuan JIA ,  Cameron BUSCHARDT ,  Lucien DUNNING ,  Brian FAHS

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F12/1009

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0664 ,  G06F12/0804 ,  G06F12/1009 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/657

Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

公开(公告)号：US20140281324A1

公开(公告)日：2014-09-18

申请号：US14134142

申请日：2013-12-19

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY ,  James M. VAN DYKE

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

Abstract translation: 本发明的一个实施例提出了一种用于将存储器页从第一存储器迁移到第二存储器的计算机实现的方法。 该方法包括确定由第一存储器支持的第一页大小。 该方法还包括确定由第二存储器支持的第二页大小。 该方法还包括基于与存储器页相关联的页面状态目录中的条目来确定存储器页面的使用历史。 该方法还包括基于第一页面大小，第二页面大小和使用历史来在第一存储器和第二存储器之间迁移存储器页面。

公开(公告)号：US20140281299A1

公开(公告)日：2014-09-18

申请号：US14133489

申请日：2013-12-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F12/08 ,  G06F12/1009 ,  G06F2212/251 ,  G06F2212/301

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

Abstract translation: 公开了用于在虚拟存储器子系统中的存储器之间转换存储器页面的技术。 统一虚拟存储器（UVM）驱动程序响应于与第一存储器页相关联的存储器访问请求来检测页面错误，其中本地页表不包括与包括在存储器访问请求中的虚拟存储器地址相对应的条目。 UVM驱动程序响应页面错误，执行页面故障序列。 页面错误序列包括将与第一存储器页相关联的所有权状态修改为中央处理单元共享。 页面错误序列还包括调度第一存储器页面以从与中央处理单元（CPU）相关联的系统存储器迁移到与并行处理单元（PPU）相关联的本地存储器。 所公开的方法的一个优点是PPU以更高的效率访问存储器页面。

公开(公告)号：US20140267334A1

公开(公告)日：2014-09-18

申请号：US14011671

申请日：2013-08-27

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06T1/60

CPC classification number: G06F11/073 ,  G06F11/0751 ,  G06T1/20 ,  G06T1/60

Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.

Abstract translation: 本发明的一个实施例包括第一处理单元在与第二处理单元共享的存储页上执行原子操作的技术。 存储器页面与对应于第一处理单元的页表项相关联。 在执行原子操作之前，包括在第一处理单元中的MMU评估包含在页表项中的原子许可位。 如果MMU确定原子许可位不活动，则两个处理单元协调更改存储器页面的许可状态。 作为状态更改的一部分，页表项中的原子许可位被激活。 随后，第一处理单元执行由第二处理单元不中断的原子操作。 有利地，通过原子许可位来协调处理单元确保原子操作的适当且有效的执行。