公开(公告)号：US20150012705A1

公开(公告)日：2015-01-08

申请号：US13935414

申请日：2013-07-03

Applicant: NVIDIA Corporation

Inventor： Peter B. HOLMQVIST ,  Karan MEHRA ,  George R. LYNCH ,  James Patrick ROBERTSON ,  Gregory Alan MUTHLER ,  Wishwesh Anil GANDHI ,  Nick BARROW-WILLIAMS

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F11/1004 ,  G06F12/0886 ,  G06F2212/1016 ,  G11C7/1006 ,  G11C7/1072

Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.

Abstract translation: 一种用于管理存储器流量的方法包括使第一数据被写入数据高速缓冲存储器，其中第一写入请求包括部分写入，并将第一数据写入数据高速缓冲存储器的第一部分，并且还包括跟踪数据高速缓冲存储器的数量 部分写入数据高速缓冲存储器。 该方法还包括如果数据高速缓冲存储器中的部分写入数大于预定的第一阈值，则向数据高速缓冲存储器发出一个或多个部分写入的填充请求。

公开(公告)号：US20140122809A1

公开(公告)日：2014-05-01

申请号：US13664387

申请日：2012-10-30

Applicant: NVIDIA CORPORATION

Inventor： James Patrick ROBERTSON ,  Gregory Alan MUTHLER ,  Hemayet HOSSAIN ,  Timothy John PURCELL ,  Karan MEHRA ,  Peter B. HOLMQVIST ,  George R. LYNCH

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0895

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

Abstract translation: 本发明的一个实施例提出了一种用于处理来自一个或多个客户端的中间缓存所接收的命令的技术。 该技术涉及从仲裁器单元接收第一写入命令，其中第一写入命令指定第一存储器地址，确定与中间缓存中包括的一组高速缓存行相关联的第一高速缓存行与第一存储器地址相关联， 使得与第一写命令相关联的数据被写入第一高速缓存行，并将第一高速缓存行标记为脏。 该技术还涉及确定在该组高速缓存行中标记为脏的总数量是否小于，等于或大于第一阈值，以及：不将脏数据通知发送到帧缓冲器逻辑，当 总数小于阈值，或者当总数等于或大于第一阈值时，将脏数据通知发送到帧缓冲器逻辑。