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    ORDER-PRESERVING DISTRIBUTED RASTERIZER
    1.
    发明申请
    ORDER-PRESERVING DISTRIBUTED RASTERIZER 审中-公开
    订购保存分配的RASTERIZER

    公开(公告)号：US20140152652A1

    公开(公告)日：2014-06-05

    申请号：US14082669

    申请日：2013-11-18

    Applicant: NVIDIA CORPORATION

    Inventor： Steven E. MOLNAR ,  Emmett M. KILGARIFF ,  John S. RHOADES ,  Timothy John PURCELL ,  Sean J. TREICHLER ,  Ziyad S. HAKURA ,  Franklin C. CROW ,  James C. BOWMAN

    IPC: G06T15/00

    CPC classification number: G06T15/005 ,  G06T2210/52

    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

    Abstract translation: 本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

    EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS
    9.
    发明申请
    EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS 审中-公开
    多线程处理单元的高效内存虚拟化

    公开(公告)号：US20140122829A1

    公开(公告)日：2014-05-01

    申请号：US13660815

    申请日：2012-10-25

    Applicant: NVIDIA CORPORATION

    Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, JR. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

    IPC: G06F12/10

    CPC classification number: G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

    Abstract translation: 一种用于同时执行多个任务的技术，每个任务具有独立的虚拟地址空间，包括为每个任务分配地址空间标识符（ASID），并且构建每个虚拟存储器访问请求以包括虚拟地址和ASID。 在虚拟到物理地址转换期间，ASID选择相应的页表，其中包括ASID和相关任务的虚拟到物理地址映射。 翻译后备缓冲区（TLB）的条目包括虚拟地址和ASID，以完成对物理地址的每个映射。 可以实现对共享虚拟地址空间的任务的深度调度，以提高对TLB和数据高速缓存的高速缓存亲和性。

    CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZATION
    10.
    发明申请
    CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZATION 有权
    用于微调缓存的控制机制用于备份存储同步

    公开(公告)号：US20140122809A1

    公开(公告)日：2014-05-01

    申请号：US13664387

    申请日：2012-10-30

    Applicant: NVIDIA CORPORATION

    Inventor： James Patrick ROBERTSON ,  Gregory Alan MUTHLER ,  Hemayet HOSSAIN ,  Timothy John PURCELL ,  Karan MEHRA ,  Peter B. HOLMQVIST ,  George R. LYNCH

    IPC: G06F12/08

    CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0895

    Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

    Abstract translation: 本发明的一个实施例提出了一种用于处理来自一个或多个客户端的中间缓存所接收的命令的技术。 该技术涉及从仲裁器单元接收第一写入命令，其中第一写入命令指定第一存储器地址，确定与中间缓存中包括的一组高速缓存行相关联的第一高速缓存行与第一存储器地址相关联， 使得与第一写命令相关联的数据被写入第一高速缓存行，并将第一高速缓存行标记为脏。 该技术还涉及确定在该组高速缓存行中标记为脏的总数量是否小于，等于或大于第一阈值，以及：不将脏数据通知发送到帧缓冲器逻辑，当 总数小于阈值，或者当总数等于或大于第一阈值时，将脏数据通知发送到帧缓冲器逻辑。

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