公开(公告)号：US09525401B2

公开(公告)日：2016-12-20

申请号：US14644637

申请日：2015-03-11

Applicant: NVIDIA Corporation

Inventor： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract translation: 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。

公开(公告)号：US10181842B2

公开(公告)日：2019-01-15

申请号：US14945377

申请日：2015-11-18

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Lingfei Deng ,  Hwong-Kwo Lin

IPC: H03K3/356 ,  H03K3/037

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

公开(公告)号：US20160269002A1

公开(公告)日：2016-09-15

申请号：US14644637

申请日：2015-03-11

Applicant: NVIDIA Corporation

Inventor： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC: H03K3/012 ,  H03K19/21 ,  H03K3/037

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract translation: 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。