公开(公告)号：US11966480B2

公开(公告)日：2024-04-23

申请号：US17654355

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Adam Hendrickson ,  Vaishali Kulkarni ,  Gobikrishna Dhanuskodi ,  Naveen Cherukuri ,  Wish Gandhi ,  Raymond Wong

IPC: G06F21/00 ,  G06F13/16 ,  G06F13/28 ,  G06F21/60 ,  G06F21/79 ,  G06N3/04 ,  H04L9/06 ,  G06F21/10

CPC classification number: G06F21/602 ,  G06F13/1673 ,  G06F13/28 ,  G06F21/79 ,  G06N3/04 ,  H04L9/0637 ,  H04L9/0643 ,  G06F21/107

Abstract: Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.

公开(公告)号：US12001592B2

公开(公告)日：2024-06-04

申请号：US17652088

申请日：2022-02-22

Applicant: NVIDIA Corporation

Inventor： Anuj Rao ,  Adam Hendrickson ,  Vaishali Kulkarni ,  Gobikrishna Dhanuskodi ,  Naveen Cherukuri

IPC: G06F21/72 ,  G06F21/60 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79

CPC classification number: G06F21/72 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79

Abstract: Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.

公开(公告)号：US20230289453A1

公开(公告)日：2023-09-14

申请号：US17654355

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Adam Hendrickson ,  Vaishali Kulkarni ,  Gobikrishna Dhanuskodi ,  Naveen Cherukuri ,  Wish Gandhi ,  Raymond Wong

IPC: G06F21/60 ,  G06F21/79 ,  H04L9/06 ,  G06F13/16 ,  G06F13/28 ,  G06N3/04

CPC classification number: G06F21/602 ,  G06F21/79 ,  H04L9/0637 ,  H04L9/0643 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/04 ,  G06F2221/0751

Abstract: Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.

公开(公告)号：US20230267235A1

公开(公告)日：2023-08-24

申请号：US17652088

申请日：2022-02-22

Applicant: NVIDIA Corporation

Inventor： Anuj Rao ,  Adam Hendrickson ,  Vaishali Kulkarni ,  Gobikrishna Dhanuskodi ,  Naveen Cherukuri

IPC: G06F21/72

CPC classification number: G06F21/72

Abstract: Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.

公开(公告)号：US11720440B2

公开(公告)日：2023-08-08

申请号：US17373678

申请日：2021-07-12

Applicant: NVIDIA CORPORATION

Inventor： Naveen Cherukuri ,  Saurabh Hukerikar ,  Paul Racunas ,  Nirmal Raj Saxena ,  David Charles Patrick ,  Yiyang Feng ,  Abhijeet Ghadge ,  Steven James Heinrich ,  Adam Hendrickson ,  Gentaro Hirota ,  Praveen Joginipally ,  Vaishali Kulkarni ,  Peter C. Mills ,  Sandeep Navada ,  Manan Patel ,  Liang Yin

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/1018 ,  G06F11/14 ,  G06F12/1027

CPC classification number: G06F11/1016 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1407 ,  G06F12/1018 ,  G06F12/1027

Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

公开(公告)号：US11698869B1

公开(公告)日：2023-07-11

申请号：US17654359

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Vaishali Kulkarni ,  Naveen Cherukuri ,  Raymond Wong ,  Adam Hendrickson ,  Gobikrishna Dhanuskodi ,  Wish Gandhi

IPC: G06F12/14 ,  G06F13/16 ,  G06F13/28 ,  G06N3/04 ,  H04L9/06

CPC classification number: G06F12/1408 ,  G06F12/1441 ,  G06F12/1458 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/04 ,  H04L9/0637 ,  H04L9/0643

Abstract: The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.